Edwin Sutanto

• Own major components of the Instruction Fetch Unit (IFU), including fetch sequencing, instruction delivery, and front-end performance tuning.
• Implement TAGE and ITTAGE branch predictors, plus a uBTB-based 1-cycle taken-branch path to improve prediction accuracy and responsiveness.
• Add Multithreading (MT) support to the IFU with thread-aware fetch scheduling and prediction-state partitionin

Instruction Fetch Unit Design Engineer
● Completed the IFU of an in house in-order ARM architecture CPU. The first, from scratch, CPU project of a new team. It’s an Aarch64 only design with Simultaneous Multithreading.
● Worked on the second generation, an out-of-order, ARM CPU. It also supports Aarch32 and Thumb32 ISAs.
● For the second project, these features were added:
o skid buffers to handl

- Developed Register Renaming Unit checker of an in house ARM architecture CPU. It checks if the correct physical registers were assigned to logical register at rename stage and checks if the correct physical registers were returned during commit, branch misprediction, or exception time.

- Developed monitoring software between core RTL and architectural checker.

2011
● Instruction Fetch and Decode Verification technical team leader. This CPU includes units to improve performance of guest ISA to host ISA translations. Instruction cache includes a primary one, and a secondary one that stores instructions at the target of a taken branch in the primary.
● Developed the test bench and BFMs in System Verilog and UVM. Wrote random test generators, including rand

● Technical team leader of Coherency and Ordering Unit (COU) verification in two Niagara family SPARC cpus. The first project used Broadcast based coherence protocol, while the second project used Directory based. Each socket consisted of 16 cores, and supported up to 8 sockets glueless cache coherence.
● Developed the testbench, some the BFMs, random test generators. The testbench can be configur

● Technical team leader of Multiprocessor Verification team for the last Pentium4 family processor.
● Owned monitoring logic between multiprocessor RTL and multiprocessor architectural checker. The checker needs Load and Store global observability time stamps to check cache coherency and/or memory ordering violations.
● Developed new or improved existing algorithms for multiprocessor checking, inc

● Worked in first Pentium4 CPU. Responsible for verifying Trace Cache fetch controller, trace build logic, and Trace Branch Prediction Unit. Wrote the verification test plans. Developed random instruction generator, including random branches and random loops.

Minor degree in Computer Science