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Aayushi PandeyAP
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Aayushi Pandey

@aayushipandey

Electronics engineering student and CirCl founder developing a student-engagement app and Verilog digital-system projects.

India
Message

What I'm looking for

I’m interested in digital system design, FSM-based architectures, and hardware modeling, and I’m strengthening my practical design and verification skills through hands-on projects.

At NIELIT Virtual Academy, I designed and simulated digital circuits using Verilog HDL, and developed modular, synthesizable code. I also gained hands-on experience with RTL design flow and hardware modeling.

As the founder of CirCl, I’m developing a student-engagement app for college activities and events with my co-founder. I take responsibility for app development, marketing, communication strategies, and user interface design, using feedback to improve the platform.

Experience

Work history, roles, and key accomplishments

CI
Current

Founder

CirCl

Jan 2024 - Present (2 years 9 months)

Spearheaded the development of an innovative app to enhance student engagement and participation. Took full responsibility for app development, marketing, communication strategies, and user interface design.

FF

Junior Organizing Team Member

FOOTPRINTS Tech Fest

Sep 2025 - Dec 2025 (3 months)

Coordinated logistics for a national-level technical festival, enhancing organizational skills. Collaborated in team management for a successful event execution, engaging with diverse teams.

NA

RTL Design Intern

NIELIT Virtual Academy

Jun 2025 - Aug 2025 (2 months)

Designed and simulated digital circuits using Verilog HDL, enhancing practical skills. Gained insights into RTL design flow and hardware modeling principles through hands-on tasks.

Education

Degrees, certifications, and relevant coursework

Maharaja Sayajirao University of Vadodara logoMV

Maharaja Sayajirao University of Vadodara

Bachelor of Engineering, Electronics Engineering

2024 -

Pursuing a Bachelor of Engineering in Electronics Engineering, with foundational experience in RTL design using Verilog HDL.

GS

Gujarat Public School

Class XII (CBSE), General

Grade: 91.4%

Completed Class XII (CBSE) with 91.4%.

GS

Gujarat Public School

Class X (CBSE), General

Grade: 97.4%

Completed Class X (CBSE) with 97.4%.

Tech stack

Software and tools used professionally

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