At Huawei Technologies, I monitor and support cloud-based Packet Core (4G/5G) infrastructure, handling incident management, fault diagnosis, and root cause analysis. I also perform system health checks, software upgrades, and preventive maintenance on Linux-based systems.
For my graduation project, sponsored by Siemens EDA under the supervision of DVT, I built a PSS model for a cache coherency example and generated stimulus for Questa Verification IP. The work explored the AMBA ACE protocol and integrating PSS with C and UVM.
I taught Verilog, VHDL, Static Timing Analysis, and Clock Domain Crossing at NTI, and assisted in digital system research and development at American University in Cairo. My projects include a UVM memory verification environment, a Verilog MIPS processor, and a C++ clinic management system.
