@yaswanthkaranam
RTL design engineer working on Verilog processor and UART designs, with verification experience across FPGA projects.
IndiaI developed a mathematical memristor window function at Indian Institute of Technology Patna, analyzing established functions and comparing performance and accuracy through MATLAB and LT SPICE implementations.
I designed a 32-bit single-cycle RISC-V processor datapath in Verilog and implemented UART and asynchronous FIFO designs. I verified these projects with self-checking testbenches, simulation, and waveform analysis.
Work history, roles, and key accomplishments
Indian Institute of Technology Patna
Dec 2025 - Feb 2026 (2 months)
Developed a mathematical memristor window function by analyzing popular window functions like Joglekar, Biolek, and Prodromakis. Implemented window functions in MATLAB and LT SPICE, and compared performance and accuracy with different window functions.
Degrees, certifications, and relevant coursework
Bachelor of Technology, Electronics and Communication Engineering
2023 -
Grade: 7.13
Pursuing Bachelor of Technology in Electronics and Communication Engineering with a CGPA of 7.13.
Certification, Memristor Modeling
2025 - 2026
Completed a certification on 'A New Window Function For Memristor Modeling' in January 2026.
Certification, FPGA Design
2025 - 2025
Completed a certification on 'Hardware Description Languages For FPGA Design' in June 2025.
Certification, Digital Design
2025 - 2025
Completed a certification on 'Fundamentals of Digital Design for VLSI Chip Design' in June 2025.
Certification, VLSI Design Verification
2025 - 2025
Completed a certification on 'Foundations of VLSI Design Verification' in July 2025.
Certification, VLSI Chip Design
2025 - 2025
Completed a certification on 'VLSI Chip Design and Simulation with Electric VLSI EDA Tool' in May 2025.
Certification, VLSI Design Verification
2025 - 2025
Completed a certification on 'Foundations of VLSI Design Verification' in July 2025.
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