Victor Hugo Padilla

At Intel Costa Rica, I led the Array Memory Product Development Engineering team supporting Xeon Server memory component development and debug. I drove technical execution, milestone tracking, team objectives, performance reviews, coaching, and alignment with product engineering priorities.

Previously at HPE, I managed 12 QA testers improving the quality and reliability of Aruba switching products. I planned test scope and switch software releases, monitored KPIs and defects, and partnered with technical teams on quality risks and release decisions.

My engineering background spans switch testing, telecom managed services, and processor product development. I've tested Layer 2 and Layer 3 networking, supported GSM and 3G platforms, troubleshot complex routing and signaling issues, and developed processor test content at Intel.

I'm a PMP-certified project management professional with a Master's Degree in Project Management and a Licentiate Degree in Electronics Engineering. I bring people leadership and technical delivery experience across semiconductor, networking, telecommunications, QA, and product engineering environments.