Looking for a job

Ponnitivalasa Manikantha

@ponnitivalasamanikan

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Aspiring RTL Design Engineer focused on VLSI, who optimized RTL timing and designed RISC-V processors.

India

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What I'm looking for

I'm seeking an RTL Design role, with a strong interest in RTL design.

At Vertex Electronics, I designed and simulated digital circuits, including SISO shift registers and an FSM, using Verilog HDL. I also optimized RTL with Synopsys Design Compiler, reducing negative slack from −10 ns to 2 ns.

I debugged ChipTop ASIC RTL, resolved design errors, and analyzed timing reports to address setup and hold violations. My work focused on reducing negative slack and improving timing performance.

In my RISC-V and UART projects, I designed processor and controller modules, developed testbenches, and verified functionality with RTL simulation. I also developed an obstacle-avoiding robot during my internship at YHills Edutech.

Experience

Work history, roles, and key accomplishments

VLSI Design Verification Intern

Vertex Electronics

May 2026 - Jul 2026 (2 months)

Designed and simulated digital circuits including SISO shift registers and FSMs using Verilog HDL. Optimized RTL to reduce negative slack from -10 ns to 2 ns using Synopsys Design Compiler and debugged ChipTop ASIC RTL to resolve design errors and timing violations.

Verilog RTL Design Functional Modeling Design Compiler Static Timing Analysis ASIC Design Debugging

Embedded Systems Intern

YHills Edutech

Jun 2025 - Aug 2025 (2 months)

Developed an autonomous obstacle-avoiding robot using Arduino UNO and an ultrasonic sensor. Programmed the robot in Embedded C to detect obstacles and automatically change direction, integrating sensor with motor control for real-time navigation.

Arduino Embedded C Ultrasonic Sensors Motor Control Robotics