Open to opportunities

JAISON JAMES

@jaisonjames

Message

I build high-speed PAM4 SerDes PHY circuits for PCIe Gen6.

India

Message

What I'm looking for

I'm looking to build high-speed analog and mixed-signal ICs, especially SerDes PHYs, where I can contribute from architecture and circuit design through silicon bring-up, validation, and PPA optimization.

At Cadence Design Systems, I've led PAM4 transmitter design for 64 Gbps PCIe Gen6 SerDes PHYs in TSMC 5nm and Intel 18A.

I've designed GM-TIA-based VGA equalization, ADC sampling pulse-generation circuits, DFE sub-blocks, injection-locked phase rotators, CML buffers, receiver-detect circuits, and a 1 GHz phase mixer for spread-spectrum clocking.

I work from architecture definition through layout-aware simulation, silicon bring-up, TX electrical validation, BER characterization, and PPA optimization, using silicon feedback to balance performance, power efficiency, and leakage.

Experience

Work history, roles, and key accomplishments

Current

Principal / Lead Design Engineer

Current

Cadence Design Systems

Sep 2016 - Present (9 years 11 months)

Led PAM4 transmitter design for 64 Gbps PCIe Gen6 SerDes PHY in TSMC 5nm and Intel 18A. Designed GM-TIA based VGA, ADC sampling pulse generation circuits, DFE sub-blocks, and injection-locked phase rotators.

Serde TSMC N6 Intel 18A GM TIA Leakage Aware Design TX Electrical Validation EDA Tools