The Microsoft Silicon Engineering and Solutions Team is seeking a Senior Silicon Design Library Verification Engineer to join their Central Front-End Tools, Flows and Methodology (TFM) group. This team drives state-of-the-art converged solutions, automation, and quality assurance checks across front-end areas. The role involves owning and maintaining design/verification IPs, managing releases, providing leadership, and working with stakeholders to collect library design requirements.
Requirements
- BS in Electrical Engineering, Computer Engineering, Computer Science, or equivalent work experience.
- 6+ years of experience in FrontEnd Digital Design and Verification.
- Well-rounded and familiar with most Front-End Tools, Flows and Methodologies.
- Strong Experience working with Verilog/SV/UVM based IP development.
- Experience with Logic Design Compilation, Simulation tools and flows
- Expertise in one of the following areas: Design compile, elaboration and filelist/libraries handling; IP packaging, release and qualification; IP integration
Benefits
- Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.