Sergej Mutas
@sergejmutas
Chip designer and project leader at Infineon, developing next-generation IGBTs, Si diodes and SiC MOSFETs for renewable energy applications.
GermanyWhat I'm looking for
At Infineon, I lead projects and design chips for next-generation IGBTs, alongside work on SiC MOSFETs and Si diodes for renewable energy applications. I hold IPMA Level C certification.
At Bosch, I supported the technology and release of automotive semiconductor ASIC products with internal and external fabs. Before that, at Apple Inc., I helped resolve manufacturing issues for VCSELs on iPhone X, enabling timely production at high yield and a successful product release.
At Apple Inc., I also worked on µLED, OLED, and VCSEL technologies. I planned and executed III-V fabrication processing and contributed to work that helped bring µLED closer to mass production.
Earlier, at Intel, I used TCAD and analytical techniques to debug chip design failures and support front-end and back-end technology development. At AMD/Globalfoundries, I led the spacer module and co-authored two patents on spacer manufacturing and characterization.
Experience
Work history, roles, and key accomplishments
Project leader and chip designer for development of next-gen IGBTs, SiC MOSFETs, and Si diodes for renewable energy applications. Holds IPMA Level C certification.
Provided technological support and release of automotive semiconductor products with internal and external fabs.
Technical project leader for atom probe tomography, responsible for training lab personnel and developing measurement procedures. Key figure between manufacturing, processing, integration, and analysis lab. Involved in III-V fabrication processing and taskforce for novel µLED structures. Helped solve major manufacturing issues for VCSELs on iPhone X, enabling high-yield production and successful p
Technical expert for atom probe tomography, responsible for training lab personnel and developing measurement procedures. Used TCAD to debug chip design failures and verify improvements. Involved in front-end and back-end technology development for 10 and 14 nm nodes.
Module leader in the spacer module for 28 and 32 nm technology. Used TCAD to decide chip design and verify manufacturability. Led collaboration between deposition, etch, and electrical characterization teams. Co-author of 2 patents for spacer manufacturing and characterization.
Education
Degrees, certifications, and relevant coursework
Technical University Berlin
Ph.D. (Doktor der Ingenieurwissenschaften, Dr.-Ing.), Nanostrukturtechnik
Ph.D. (Dr.-Ing.) under Prof. Dr. John Banhart, focusing on analysis of high-k materials and metal gates for 28 and 32 nm technology nodes.
Julius-Maximilians-Universität Würzburg
Diploma (M.A.) (Diplom Ingenieur Universität), Nanostrukturtechnik
Diploma (M.A.) in Nanostrukturtechnik under Prof. Dr. A. Forchel, including a collaboration with IBM Almaden Research Center.
Tech stack
Software and tools used professionally
Availability
Location
GermanyAuthorized to work in
Salary expectations
Social media
Job categories
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