At Hochschule für Angewandte Wissenschaften München, I research NoC and chiplet interconnect generator design for scalable hardware development. My work explores irregular Networks-on-Chip and modular systems that account for bandwidth, QoS, fault tolerance, and reliability.
At Infineon Technologie AG, I analyzed designs related to timing signoff and modeled a Gigabit Ethernet module in SystemC. I implemented simulation models and test cases for automotive microcontroller applications, then evaluated test results and performance.
My projects have included regulating memory bandwidth in a RISC-V multicore softcore processor to reduce interference between cores, and programming an NXP LPC4357 dual-core microcontroller in C for an electronically controlled load. I also developed and evaluated a hardware-in-the-loop test system for embedded devices at MTU/ Rolls Royce Power System AG.
