Open to opportunities

Anand K Vinu

@anandkvinu

Message

I extend LLVM for custom RISC-V processors and packed SIMD acceleration.

India

Message

What I'm looking for

I'm looking to build compiler and architecture solutions for RISC-V systems, especially LLVM backend development, ISA extensions, compiler optimization, and hardware–software co-design.

At the MeitY RISC-V Project at CUSAT, I extended the LLVM RISC-V backend for custom Packed SIMD and Bitmanip ISA extensions, building support across TableGen, intrinsics, SelectionDAG, GlobalISel, FunctionPasses, and bare-metal Clang/LLVM toolchains. My compiler work reduced executed instruction/cycle count by approximately 30% and generated code size by 12.7% through validation on Spike.

I've also led embedded and system architecture work for the Horizon Mars Rover Team, which achieved 18th global rank at the 2024 European Rover Challenge, and developed firmware and hardware control circuitry for an educational CNC machine at Super FabLab. I enjoy compiler–architecture co-design, from RISC-V microarchitecture and packed SIMD concepts to efficient compiler lowering and validated machine code.

Experience

Work history, roles, and key accomplishments

Compiler Engineer / Project Associate

MeitY RISC-V Project, Government of India, CUSAT

Aug 2024 - Mar 2026 (1 year 7 months)

Extended the LLVM RISC-V backend with custom Packed SIMD (ZPN) and Bitmanip ISA extensions, implementing instruction definitions and lowering across TableGen, intrinsics, SelectionDAG, and GlobalISel. Developed LLVM FunctionPasses for pattern recognition and packing, and validated bare-metal toolchains on Spike, achieving ~30% reduction in executed instruction/cycle count and 12.7% smaller code.