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A K Vishwa

@akvishwa

Embedded systems and RF design student who simulated X-band metasurface absorbers with over 90% absorptivity in CST Studio Suite.

India

Message

I designed and simulated an X-band metasurface absorber using CST Studio Suite, achieving over 90% absorptivity with simulated S11 minima near -28 dB at 8.7 GHz and 11.2 GHz.

During my Embedded Systems Intern training at Pantech.AI Solutions, I worked with 8051, ARM, Cortex-M4, PIC, and NodeMCU platforms using Keil. I also trained in UART, SPI, and I2C interfacing and studied RTOS concepts and IoT protocols.

At Emertxe Information Technologies, I developed C-based microcontroller applications and built an end-to-end IoT system following the SDLC. My projects also include an 8051-based industrial monitoring system and an 8-bit ALU designed with Verilog HDL.

Experience

Work history, roles, and key accomplishments

VLSI Design Training

Ajay Kumar Garg Engineering College

Jun 2026 - Aug 2026 (2 months)

Analyzed NMOS and PMOS characteristics and designed a CMOS inverter standard-cell layout using Cadence Virtuoso. Performed layout verification through DRC and LVS while following CMOS design rules.

Virtuoso CMOS Layout Design DRC LVS

Embedded Systems Intern

Pantech.AI Solutions

Feb 2026 - May 2026 (3 months)

Trained in Embedded System Design and IoT on 8051, ARM, Cortex-M4, PIC, and NodeMCU using Keil, with UART, SPI, I2C, LCD, relay, and switch interfacing. Studied the embedded product life cycle, real-time concepts, RTOS, debugging tools, and IoT architecture and protocols.

Embedded C 8051 ARM Cortex M PIC NodeMCU Keil UART SPI I2C LCDs Relay RTOS IoT

IoT Intern

Emertxe Information Technologies

Aug 2025 - Oct 2025 (2 months)

Developed C-based microcontroller applications and gained practical knowledge of Embedded Systems. Built an end-to-end IoT system following the Software Development Life Cycle (SDLC).

Embedded C Microcontrollers IoT SDLC