Abdalah adan

I’m a Physical Design Engineer with 4+ years at IBM, delivering full RTL-to-GDS flows on advanced nodes (3nm, 5nm). I own end-to-end delivery for functional blocks—from floorplanning through timing closure, DRC/LVS signoff, and tapeout—backed by strong power analysis and automation depth.

At IBM, I delivered one successful tapeout while ramping up quickly and absorbing additional blocks from other teams. I owned floorplanning and SDC definition for 23 functional blocks, resolving IP placement errors early and partnering with IP teams to prevent major rework downstream.

I led timing closure across all 23 blocks through clock tree balancing, CTS tuning, and useful skew, achieving convergent signoff and delivering phase exit milestones a week ahead of schedule. I also applied latch attraction studies across 7 blocks to shorten critical signal paths and improve macro utilization, meeting ACE routability targets before handoff.

Beyond signoff, I’ve driven power and debug efficiency: I accelerated team adoption of a new power optimization tool, reduced L2 cache power by ~151 mW, and leveraged an in-house AI engineering tool during DRC/LVS signoff to triage logs and distinguish localized vs. systemic violations—improving debug cycle efficiency by ~9%.