Open to opportunities

Mac Chester

@macchester

Message

I validate CPU/SoC memory subsystems and solve complex DRAM debug issues.

United States

Message

What I'm looking for

I'm looking for a long-term role with an innovative, dynamic organization that values autonomy, mastery, meaningful day-to-day work, collaboration, and complex technical projects.

At Intel, I validate client CPU/SoC memory subsystems using DDR5 and LPDDR5 devices from major DRAM vendors. I deliver post-silicon memory controller debug from power-on through qualified product release.

I work across taskforces to resolve showstopper memory interface problems, drive root-cause fixes with customer platforms, and apply shift-left methods to improve future designs.

Across two decades in semiconductors, including Micron and Inapac Technology, I’ve led high-volume manufacturing ramps, designed and validated probe and test hardware, optimized test code, and supported custom mobile-DRAM products.

Experience

Work history, roles, and key accomplishments

Current

Senior Memory Functional Validation Engineer

Current

Intel

Feb 2021 - Present (5 years 7 months)

Responsible for functional validation of cutting-edge client CPU/SoC memory subsystems using DDR5 and LPDDR5 devices. Assists multiple taskforces to drive solutions for memory interface problems and delivers post-silicon memory controller debug from power-on to product release.

DDR5 LPDDR5 CPU Memory Validation Debugging Python Perl C C++Verilog JMP Git Jira Confluence ATE Advantest Teradyne Pyramid

Senior Test Engineer

Micron Technology

Nov 2009 - Jan 2021 (11 years 2 months)

Planned and executed high-volume manufacturing ramps for R&D first-of-a-kind specialty HBM memory products and mobile DRAM products. Designed and validated probe and test hardware, developed cost reduction strategies, and implemented Best Known Methods.

HBM DRAM Test Engineering Probe Hardware Testing Cost Reduction Best Known Methods Test Code Optimization