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Hasita Yadavalli

@hasitayadavalli

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I build and validate digital design projects using Verilog, Cadence, Java, and structured documentation.

India

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What I'm looking for

I'm looking for an entry-level role where I can apply my technical, documentation, and analytical skills while learning new technologies, sourcing tools, Boolean search, recruiting workflows, and structured processes.

I've built and tested digital logic circuits using Verilog HDL and Cadence, including a full adder design where I analyzed simulation results and documented findings.

At the Central Institute of Tool Design in Hyderabad, I supported simulation, analysis, and validation of standard cell designs. I followed structured processes to record observations on timing, functionality, and design efficiency.

During my Java and GitHub internship at SWECHA Learning Academy, I learned OOP, exception handling, collections, and version control while collaborating on assigned project activities.

I'm a B.Tech Electronics and Communication Engineering graduate who brings organized documentation, analytical thinking, attention to detail, and a willingness to quickly learn new technologies and workflows.

Experience

Work history, roles, and key accomplishments

Standard Cell Design Intern

Central Institute of Tool Design

Mar 2021 - May 2021 (2 months)

Supported technical project work involving simulation, analysis, and validation of standard cell designs using Verilog HDL. Followed structured instructions and documented observations related to timing, functionality, and design efficiency.

Verilog Simulation Analysis Validation Documentation

Education

Degrees, certifications, and relevant coursework

K G Reddy University of Technology and Engineering

Bachelor of Technology, Electronics and Communication Engineering

Pursued a Bachelor of Technology in Electronics and Communication Engineering, gaining foundational knowledge in electronics and communication systems.