At Texas Instruments, I designed an automated crystal characterization platform for Oscillation Allowance testing across HFXT and LFXT crystal oscillators. I built custom test PCBs and a Python GUI for automated PVT sweeps, and analyzed phase noise for an M0 device.
As a Research Intern at NIT Trichy, I designed and simulated five parallel-prefix adder architectures in Verilog, then proposed and implemented a custom 4-operand adder with O(log₂ n) delay. I also developed an EcoMenderBot on a DE0-Nano FPGA, integrating a multi-cycle RISC-V CPU, sensors, and path planning.
