In short, we connect chips to create powerful and energy-efficient networks, overcoming connectivity limitations in the semiconductor industry. We deliver the graphene solutionBlack Semiconductor is looking for a Senior Advanced Packaging Architect (f/m/d) to join our photonics product development team. In this pivotal role, you will architect the next generation of advanced packaged SOCs incorporating advanced CMOS processes and latest photonics innovation targeting data centers and edge AI use cases
You will be responsible for designing and implementing advanced packaging solutions for high-performance heterogeneous, silicon and photonics, SOCs using chiplet architecture. You will be foundry and OSAT interface person for advanced packaging vendor evaluation, technology selection, feasibility study, design, manufacturing, assembly, test, and qualification
- Fully documented SOC Advanced Packaging Product Requirement Specification (PRS) per product that includes package design, verification, thermal/mechanical analysis, quality/reliability and estimations for performance and cost
- Fully documented advanced packaging IP roadmap aligned with our technology capabilities and OSATs
- Fully documented Customer Packaging Requirement Document (CRD) per customer engagement
- Advanced Packaging concept and feasibility documents that describe the solution space explored and recommendation on final architecture
- Fully documented advanced packaging ecosystem and competitive analysis
- Bachelor’s degree in Electrical Engineering, Mechanical Engineering, or Materials Science is required; Master’s or PhD preferred
- 10+ years of experience in semiconductor packaging with a focus on advanced techniques such as 2.5D/3D integration, fan-out packaging, or system-on-chip (SoC) solutions
- 10+ years of experience with 2.5D/3D/3.5D heterogeneous integration technologies such as SoIC, CoWoS, WoW, and Photonics
- 10+ years of experience in advanced packaging and organic substrate technology, silicon, interposer, substrate manufacturing process, assembly flow, functional and reliability test, and qualification
- 10+ years of experience with wafer bumping, package assembly, substrate technology, BOM selection, testing, and product development lifecycle
- 10+ years of experience in understanding core and build-up material mechanical/electrical properties, trade-offs, CTE mismatch, TSV impact on warpage, stress, reliability, and Chip Package Interaction (CPI)
- Understanding of current silicon photonics packaging and connectivity
- Successful customers engagement on so-architecting customer specific solutions