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RAVINDRA SINGH

@ravindrasingh6

IP/SoC design verification consultant at Logixchip Technologies, verifying AI compute SoCs and die-to-die interconnects.

Ireland

Message

At Logixchip Technologies, I define verification plans and testbench architecture for AI compute SoC blocks, including interconnects and reset trees. I verify AMBA interconnect traffic and die-to-die subsystem functionality.

At Intel, I developed IP-level testbench features and verified packet scheduler, traffic shaper, and host interface RAS blocks. I also checked performance requirements and implemented functional coverage.

At Xilinx Asia Pacific Pte. Ltd., I worked on Versal FPGA SoC verification, including processor boot-up, C-code execution, NoC topology, and the Platform Management Controller. I also verified Boot ROM and firmware interfaces and PCIe partial reconfiguration.

Earlier, at Cadence Design System and Mentor Graphics, I developed assertion-based verification IP for standard protocols and supported formal verification. My work has included UVM and SystemVerilog testbenches, formal methods, and protocols such as AMBA, DFI, and CPRI.

Experience

Work history, roles, and key accomplishments

Current

IP/SoC Principal Design Verification Consultant

Current

Logixchip Technologies

Mar 2025 - Present (1 year 7 months)

Defined verification plans and testbench architectures for AI Compute SoC and Die-to-Die subsystems. Verified AMBA interconnects, reset trees, and PHY training sequences, achieving 100% functional coverage closure.

UVM Methodology SystemVerilog AXI AXI5 APB Cadence JasperGold Python Perl Shell Makefiles Functional Coverage Constraint Random Verification

Senior Staff Design Engineer

Intel

Jan 2022 - Feb 2025 (3 years 1 month)

Developed IP-level testbenches for Packet Scheduler Module, Traffic Shaper, and HIF Core-RAS. Defined verification plans and testbench architectures, implemented constrained random test cases, and achieved 100% functional coverage closure.

UVM Methodology SystemVerilog VIP Development Functional Coverage Constraint Random Verification Python Perl Shell Makefiles

Senior Staff Design Engineer

Infineon Technologies

Oct 2020 - Jan 2022 (1 year 3 months)

Developed subsystem-level testbenches for LPDDR4 Memory Controller and PHY. Verified AXI4 and AHB interfaces, memory controller throughput, and priority/arbitration schemes, achieving 100% functional coverage closure.

UVM Methodology SystemVerilog AXI AHB LPDDR4 Memory Controller Physics Functional Coverage Constraint Random Verification Python Perl Shell Makefiles

Staff Design Engineer

Xilinx Asia Pacific Pte. Ltd.

Feb 2018 - Sep 2020 (2 years 7 months)

Owned SoC-level testbench development for Versal FPGA, including processor boot-up sequences, C-code execution, and VIP integration. Verified PMC, NoC, HSC, Boot ROM, and PCIe blocks, and performed formal verification of GPIO and IO Mux connectivity.

UVM Methodology SystemVerilog NOC PCIe DDR4 CCIX Formal Verification Cadence JasperGold Python Perl Shell Makefiles Functional Coverage

Principal R&D Engineer

Cadence Design Systems

Mar 2015 - Jan 2018 (2 years 10 months)

Led ABVIP and CSR-PA product development using Agile Scrum. Developed assertion-based VIP for AMBA and memory protocols, and provided global customer support for formal verification.

SystemVerilog SVA PSL+ABVIP Formal Verification Cadence JasperGold Siemens OneSpin Agile Scrum IP XACT DFI DDR LPDDR

Lead SoC/ASIC Verification Engineer

Ericsson

Nov 2013 - Feb 2015 (1 year 3 months)

Defined verification plans and testbench architectures for CPRI subsystem. Verified CPRI, AXI interconnect, and ARM Cortex-M4 functionality, and developed UVCs for high-speed interfaces.

UVM Methodology SystemVerilog CPRI AXI ARM Cortex M UVC Tracking Functional Coverage Constraint Random Verification

Senior Design Engineer

Freescale Semiconductor

Jun 2012 - Nov 2013 (1 year 5 months)

Verified Ethernet, SIUL, and SoC synchronizer flops for automotive SoC. Performed formal verification of GPIO and IO Mux connectivity, and implemented testbenches with functional coverage.

UVM Methodology SystemVerilog Ethernet RMII MII Formal Verification Functional Coverage Perl Shell Makefiles

Lead Member Technical Staff

Mentor Graphics

Oct 2010 - Jun 2012 (1 year 8 months)

Developed and enhanced UVC/VIP for AMBA protocols using SystemVerilog and UVM. Created SVA-based formal verification IP and Accellera OVL libraries, and provided customer support.

UVM Methodology SystemVerilog AHB AXI APB OCP SVA PSL+Formal Verification OVLA

Senior Design Engineer

STMicroelectronics

May 2007 - Jul 2010 (3 years 2 months)

Verified protocol bridges and NoC interconnect clusters. Developed testbenches from scratch using SystemVerilog/UVM and Specman-e/eRM, and implemented NoC protocol eVC/VIP.

UVM Methodology SystemVerilog Specman ERM NOC AXI AHB STBus VSTNoC Functional Coverage Constraint Random Verification Perl Shell Makefiles

Project Engineer

Wipro Technologies

Jun 2006 - Jan 2007 (7 months)

Verified memory controller block using Specman-e and eRM methodology. Integrated Denali memory models and implemented checkers and functional coverage.

Specman ERM Memory Controller DDR SRAM ROM Functional Coverage Constraint Random Verification Perl Shell Makefiles

Education

Degrees, certifications, and relevant coursework

Motilal Nehru National Institute of Technology

Bachelor of Technology, Electronics and Communications Engineering

Grade: 8.21/10

Bachelor of Technology in Electronics and Communications Engineering from Motilal Nehru National Institute of Technology, Allahabad, completed in 2006.