Ravindra Singh

Developed subsystem-level testbench in UVM/SV for Die to Die IP, including VIP integration, drivers, monitors, and checkers. Defined verification plans and implemented functional coverage closure.

Verified infrastructure processing unit IPs including Packet Scheduler Module, Traffic Shaper, and HIF Core-RAS. Developed testbenches, defined verification plans, and achieved 100% functional coverage closure.

Verified LPDDR4 memory controller and PHY subsystem, including VIP integration, performance checking, and memory controller arbitration schemes. Achieved 100% functional coverage closure.

Performed SoC-level functional verification of Versal FPGA, including boot-up sequences, NoC topology, and PCIe partial reconfiguration. Automated regression and reporting using scripting languages.

Developed and managed Assertion-Based Verification IP (ABVIP) and CSR-PA formal flow products. Provided global customer support and led team using Agile Scrum methodology.

Verified CPRI subsystem for next-generation radio, including ARM Cortex-M4 and AXI interconnect. Developed testbenches from scratch and led a team of four engineers.

Verified Ethernet and SIUL IP for automotive SoC, including formal verification of GPIO and IO Mux connectivity. Implemented testbenches and regression automation.

Developed AMBA protocol VIPs and assertion-based VIPs for formal verification. Provided global customer support and implemented test suites.

Verified NoC protocol bridges and interconnect clusters, developing testbenches from scratch using SystemVerilog/UVM and Specman-e. Implemented monitors, checkers, and functional coverage.

Verified memory controller block using Specman-e and eRM methodology, integrating Denali memory models and implementing checkers and functional coverage.

Grade: 8.21/10

Bachelor of Technology in Electronics and Communications Engineering from Motilal Nehru National Institute of Technology Allahabad, completed in 2006.