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Quoc NguyenQN
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Quoc Nguyen

@quocnguyen1

Physical Design intern at GUC who implemented a pipelined RISC-V core reaching 107.14 MHz.

Vietnam
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What I'm looking for

I’m looking for a Physical Design internship where I can learn, improve my skills, and apply my knowledge in practice. I hope to continue working at the company after my internship.

At GUC, I worked as an Engineer Intern from January to May 2026. I’m a final-year electrical and electronics student seeking an internship in Physical Design to learn and apply my knowledge in practice.

For my ICTC Fundamental Physical Design Course capstone, I designed a five-stage pipelined RISC-V core with hazard detection and forwarding, extending RV32I for Galois Field arithmetic. The pipelined core reached a maximum operating frequency of 107.14 MHz on an FPGA DE10.

In my ICTC Fundamental Physical Design Course final project, I synthesized a design and ran place and route in Cadence Innovus. I performed static timing analysis and iterated on fixes, with post-route timing close to the stated WNS/TNS goals.

My electrical and electronics studies, university lab work, and private consulting helped me develop interpersonal skills. I hope to continue working at a company after an internship.

Experience

Work history, roles, and key accomplishments

GUC logoGU

Engineer Intern

Jan 2026 - May 2026 (4 months)

Worked as Engineer Intern at GUC.

ICTC Fundamental Physical Design Course logoIC

Capstone project

Jan 2026 - May 2026 (4 months)

Design of RISC-V (RV32I) Instruction Set Extension for Galois Field Processing

Researched and extended the base RV32I Instruction Set Architecture to support

Galois Field arithmetic, specifically for cryptographic and error-correction

applications

Designed and implemented a 5-stage pipelined RISC-V CPU core featuring Hazard

Detection and Forwarding Units to optimize performance

Implemented t

ICTC Fundamental Physical Design Course logoIC

Final Project

Aug 2025 - Nov 2025 (3 months)

Fill-in all input data (netlist, sdc, tech lef, lib,...)

Synthesized & ran P&R in Cadence Innovus, built PG mesh; timing-driven

placement, CTS with skew targets, fix DRV (max caps, max fanouts)

Performed STA with CRPR; iterated fixes (buffer insertion/useful skew); routed &

cleaned DRC/antenna.

Timing at postRoute goal: WNS/TNS close to 0.03ns/0.3ns, core utilization ~65%,
fmax ~200 MHz

Trung Tâm Đào Tạo Vi Mạch ICTC logoTI

Fundamental Physical Design Course

Jul 2025 - Oct 2025 (3 months)

Worked as Fundamental Physical Design Course at Trung Tâm Đào Tạo Vi Mạch ICTC.

Education

Degrees, certifications, and relevant coursework

HH

Ho Chi Minh City University of Technology (HCMUT)

Telecommunications Engineering

HT

Ho Chi Minh City University of Technology

Baccalauréat en ingénierie, Electrical and Electronics Engineering

2021 - 2026

Tech stack

Software and tools used professionally

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