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Jerome Awad

@jeromeawad

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Software engineer at Lorentz Kracht who developed Verilog code to negate delay-Doppler effects.

Australia

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What I'm looking for

I'm a Computer Engineering graduate from RMIT University with a strong passion for technology, software development, and continuous learning. I'm looking for opportunities to apply my software development skills and keep learning new technologies.

At Lorentz Kracht, I developed Verilog code to negate delay-Doppler effects for a wireless communications start-up. I also contributed to client planning and requirements gathering, and tested and debugged the work.

For the Delay-Doppler Solution project, I implemented OTFS-based modulation on FPGA to mitigate distortion in high-mobility channels and improve Doppler robustness and link reliability.

At RMIT, I built and launched the Climate Change Display, a content site that retrieves article URLs and connects articles that reference one another.

I also developed QNX client-server applications using Raspberry Pis as simulated traffic lights to demonstrate IPC communications. My background includes computer and network engineering, computer science, and software development with Java, C++, and Python.

Experience

Work history, roles, and key accomplishments

Current

Associate Parts Broker

Current

OEConnection

Jun 2026 - Present (5 months)

Assessed challenged price requests by analyzing OEM, aftermarket, and recycled parts pricing to determine competitive solutions. Prepared accurate parts quotations and processed customer orders with high accuracy.

Pricing Analysis Customer Service Order Processing Communication Skills Collaboration

Sales Assistant

YD.

Jan 2021 - Mar 2026 (5 years 2 months)

Communicated with customers to understand needs and provide personalized styling advice. Managed stock and maintained store standards.

Customer Service Communication Skills Stock Management Styling

Software Engineer

Lorentz Kracht

Feb 2025 - Dec 2025 (10 months)

Developed Verilog code to negate delay-doppler effects. Collaborated in client meetings and conducted testing and debugging for high-quality delivery.

Verilog FPGA Testing Debugging Collaboration