Jakob Young
@jakobyoung1
I design Verilog CPUs and embedded hardware-software systems.
CanadaWhat I'm looking for
I've designed and implemented a custom RISC CPU in Verilog, including instruction decoding, register operations, and ALU functionality. I validated its functionality with testbenches and waveform debugging.
I'm pursuing Computer Engineering at Queen's University and have built and tested audio amplifier circuits using analog design principles, oscilloscopes, and signal generators. As a Maintenance Team Supervisor at Brentwood College School, I've led daily operations, coordinated with department heads, and directed employees through work orders.
Experience
Work history, roles, and key accomplishments
Maintenance Team Supervisor
Brentwood College School
Jun 2021 - Aug 2026 (5 years 2 months)
Directed a team of employees, efficiently processing work orders to maintain productivity. Led daily maintenance operations for school facilities and grounds, and managed communication between the maintenance team and department heads.
Education
Degrees, certifications, and relevant coursework
Queen's University
Bachelor of Applied Science, Computer Engineering
Pursuing a Bachelor of Applied Science in Computer Engineering with an expected graduation in May 2028. Recipient of a scholarship.
Availability
Location
CanadaAuthorized to work in
Salary expectations
Social media
Skills
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