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Waleed Malik

@waleedmalik1

Silicon Design Engineer II at AMD who cut chip verification test runtimes by 98% with an automated testbench.

At AMD, I wrote and debugged Python and SystemVerilog/UVM automation for chip verification, including checkers, monitors, and testbench infrastructure. I built an automated testbench that cut per-test runtime by 98%, from 50 minutes to 2 minutes.

I also introduced an AI-assisted debug workflow that reduced development and debug timelines from 12 weeks to 6 weeks, and automated 90% of testbench creation, testing, and debug review. I received an internal AI Spotlight award for this work.

Earlier at AMD, I built and maintained scripts for RTL sanity, regression, and coverage testing, and shipped a new internal tooling flow that replaced a 10-year-old testing system. At McMaster University, I taught tutorials on software testing and computer networks and security.

Experience

Work history, roles, and key accomplishments

Current

Silicon Design Engineer II

Current

AMD

May 2025 - Present (1 year 5 months)

Wrote and debugged Python and SystemVerilog/UVM automation for chip verification, including checkers, monitors, and testbench infrastructure. Built a new automated testbench that cut per-test run-time by 98% and introduced an AI-assisted debug workflow.

Python SystemVerilog UVM Methodology Perl BASH Git Jenkins Perforce Unix Linux CI CD AI Assisted Debugging Tools

Computer Networks and Security Teaching Assistant

McMaster University

Jan 2025 - Apr 2025 (3 months)

Led tutorials and labs using Cisco Packet Tracer, instructing students on network configuration, security protocols, and troubleshooting techniques for routers and switches.

Cisco Packet Tracer Network Configuration Security Protocols Troubleshooting

Software Testing Teaching Assistant

McMaster University

Jan 2025 - Apr 2025 (3 months)

Delivered biweekly tutorials on unit testing and regression testing on Java-based programs using JUnit, guiding students through test-driven development and debugging strategies. Taught branch and statement coverage analysis with EclEmma.

Java Junit Test Driven Development EclEmma Debugging

Silicon Design Engineer I

AMD

May 2023 - Aug 2024 (1 year 3 months)

Set up and maintained AMD IP Design Verification flow, executing and monitoring test plans, conducting functional verification, and debugging setup issues. Built and maintained Python and Perl scripts to automate RTL sanity, regression, and coverage testing flows.

Python Perl C Shell Jenkins Perforce RTL Verification CI CD Caching