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Foez Ahmed

@foezahmed

Lead RTL Design & Verification Engineer at ADN Semiconductors, defining DDR controller microarchitecture and AXI integration.

Bangladesh

Message

At ADN Semiconductors, I define the microarchitecture and data-handling architecture for a custom DDR controller and its AXI integration into the SoC. I provide technical direction for an approximately 50-engineer team and contribute to RISC-V projects and FPGA emulation.

At Dynamic Solution Innovator Ltd., I was technical lead for architecture and verification of a quad-core RV64GV SoC that taped out on 12 nm with a 1.5 GHz target. I also developed a reusable class-based AXI4 Master/Slave VIP and owned a custom directory-based cache coherence protocol from definition through verification.

Experience

Work history, roles, and key accomplishments

Current

Lead Engineer, RTL Design & Verification

Current

ADN Semiconductors

Jan 2026 - Present (9 months)

Define the microarchitecture and data-handling architecture of a custom DDR controller IP and its AXI integration into the SoC. Provide technical direction for a team of approximately 50 engineers and lead architectural, functional, and RTL/design reviews.

RTL Design Verification Memory Controller AXI Microarchitecture SOC FPGA Emulation RISC V

Engineer, RTL Design & Verification

Dynamic Solution Innovator Ltd.

Jan 2022 - Jan 2026 (4 years)

Technical lead for architecture and verification of a quad-core RISC-V SoC, including interconnect architecture, verification flow, and FPGA emulation. Developed a reusable AXI4 Master/Slave VIP and owned a custom directory-based coherent cache system end to end.