Eric Hamel
@erichamel
I build and verify FPGA, ASIC, and high-speed hardware for radios, aerospace, networking, and test systems.
CanadaWhat I'm looking for
I'm currently restoring and debugging a MIL-STD-1553 modem FPGA flow at Edgewater Computing Systems, including Linux development, legacy testcases, RTL, inferred memories, DSP rewrites, and Microchip PolarFire flow changes.
Across Syntronic engagements, I delivered FPGA, board, and high-speed interconnect work for Intel 5G radios, MDA, Amazon Robotics, Natus Systems, and X-Sensor. My work has included DDR record/playback, TDD timing, 25.4 Gbps JESD204B interconnects, Smart Camera processor cards, robot backplanes, analog front ends, and signal-detection correlators.
I've built and verified control FPGAs for Neptec's Tridar system, modernized the MAP300 FPGA flow at Viavi, and developed Ethernet multicast capabilities at Rockport Networks. At Huawei, I worked on full-duplex and Massive MIMO radios, including JESD interfaces, MicroBlaze control, SPI, board bring-up, RTL, verification, and schematics.
Earlier, I brought wireless jammers, blast sensors, low-power wireless ASICs, Bluetooth platforms, satellite-phone testers, and telecom hardware from design through validation and production. I combine RTL, UVM/SystemVerilog verification, DSP modeling, high-speed board design, lab debugging, and automation to solve practical product problems.
Experience
Work history, roles, and key accomplishments
Senior FPGA / Hardware Engineer
Syntronic Canada
Feb 2021 - Oct 2025 (4 years 8 months)
Integrated packet switch into Intel's PTP design, designed TDD timing modules, and automated pin verification for FPGA frameworks.
Senior Staff System Electronics Design Engineer
Neptec Design Group
Oct 2019 - Jul 2020 (9 months)
Designed and verified control FPGA for Tridar Aerospace positioning system, including AHB arbiter, DMA, and telemetry algorithms.
Contractor FPGA/ SW Engineer
Viavi Solutions
Apr 2019 - Oct 2019 (6 months)
Reverse engineered legacy FPGA code, implemented clock domain crossing, and cleaned up timing constraints for MAP300 product.
FPGA/ SW Engineer
Rockport Networks
Sep 2017 - Jan 2019 (1 year 4 months)
Implemented Ethernet broadcast function in FPGA, verified multicast features with SystemVerilog, and debugged using WireShark.
FPGA/SW/HW Engineer
Huawei
Aug 2015 - Sep 2017 (2 years 1 month)
Designed FPGA for full duplex radio and massive MIMO radio, including JESD interfaces and Microblaze processor integration.
FPGA Engineer
Allen Vanguard
Jan 2006 - Dec 2014 (8 years 11 months)
Implemented FPGA modules in VHDL for wireless jammer, including DSP equations and verification environments.
Project Engineer
Allen Vanguard
Jan 2011 - Dec 2013 (2 years 11 months)
Implemented digital portion of blast sensor circuit and FPGA, brought product to production.
ASIC Engineer
Kleer Semiconductor
Jan 2002 - Dec 2006 (4 years 11 months)
Designed and verified ASIC modules for low power wireless transceiver, including AGC, RSSI, and sequencer.
ASIC Engineer
IceFyre Semiconductor
Jan 2001 - Dec 2002 (1 year 11 months)
Designed ASIC modules in Verilog for WLAN PHY, wrote automation scripts in Perl and TCL for logic equivalency check.
Hardware Design Staff Engineer
Conexant Systems
Jan 1999 - Dec 2001 (2 years 11 months)
Designed Bluetooth baseband development platform and FPGA firmware/hardware for DDS demo.
Lead AEC Hardware Engineer
Anritsu
Jan 1997 - Dec 1999 (2 years 11 months)
Designed and brought to production Globalstar Baseband Module, leading to over 200 tester sales.
Hardware Engineer
NEC America
Jan 1996 - Dec 1997 (1 year 11 months)
Designed FPGA for PC/PCS RF module development interface and supported CDMA cellular phone digital portion.
Hardware Engineer
SR Telecom
Jan 1995 - Dec 1996 (1 year 11 months)
Designed various PCBs including echo canceller, data card, and line card, and wrote procedures for ISO-9000 accreditation.
Education
Degrees, certifications, and relevant coursework
Université de Sherbrooke
Bachelor of Science, Electrical Engineering
Bachelor of Science in Electrical Engineering with a major in Computer Engineering, completed through a co-op program in 1994.
Collège Édouard-Montpetit
Diploma, Pure and Applied Sciences
Diploma in Pure and Applied Sciences from Collegian Diploma Studies, completed in 1990.
Udemy
Online Course, SystemVerilog and UVM
Completed online courses in SystemVerilog and UVM verification methodologies.
Institut Mines-Télécom
Online Course, Network Fundamentals
Completed online courses in 5G and 4G Network Fundamentals via Coursera.
Cisco Networking Academy
Online Course, Data Communication and Network Services
Completed online courses in Data Communication and Network Services via Coursera.
Cisco Networking Academy
Online Course, Network Protocol and Architecture
Completed online course in Network Protocol and Architecture covering Ethernet and IPv4 via Coursera.
Availability
Location
CanadaAuthorized to work in
Salary expectations
Job categories
Skills
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