Deepan Kumaar User

I've built and prototyped RISC-V-based SoCs at Shakra Innovations, using SHAKTI's C-Class Vajra core for an IoT gateway validated on Arty A7-100T and Nexys Video FPGA boards.

I ported SHAKTI's E-Class SoC to a custom Lattice Certus-NX board by replacing Xilinx-specific IP and developing custom Verilog IP. I also created FPGA bitstreams and supported participants with driver integration and SDK use during a 48-hour Shakti FPGA Hackathon.

At Tampere University, I analyzed signal-processing data with Python while pursuing an MSc in Computing Sciences and Electrical Engineering focused on System-on-Chip Design.

I'm developing a SystemVerilog CNN accelerator with parallel processing elements, signed 8-bit data handling, AXI memory mapping, and Ibex RISC-V SoC integration. My work also includes AXI DMA, I2C, SPI, UART, pipelined ripple-carry adders, and optimized FFT implementations.