Anand Mohan

Owned NT98528 SoC firmware bring-up as project in-charge, leading a 9-engineer cross-functional team and improving milestone delivery from ~50% delays to 90%+ on-time execution. Built an end-to-end OP-TEE Secure Boot chain of trust with zero chain-of-trust failures across 50 boot cycles and cut build effort 120 hrs to 40 hrs (66%), while reducing Web UI video latency from 8s to 250ms.

Served as Feature Architect for a dual-processor non-HCI Bluetooth platform (FreeRTOS + MCU + CSR Virtual Machine), driving software-hardware co-design across multiple sensor/peripheral stacks. Optimized FreeRTOS scheduling and inter-processor I2C communication to resolve race conditions, improving MTBF from 8 hrs to 120 hrs, while using Jenkins automation to reduce integration effort ~65% and pro

Redesigned Class C medical firmware architecture under IEC 62304 using modular C++ and QP/QM RTEF state machines across 12+ subsystems, achieving first-pass compliance with zero non-conformances across 4 external safety audits. Cut firmware iteration cycles from 16 days to 6 days and reduced open safety-critical defects from 38 to 3 while expanding test coverage from 127 to 450+ fault-injection ca

Owned avionics verification across 4 software projects and 150+ DO-178C functional requirements, maintaining transparent milestone updates to Boeing stakeholders. Built Python automation integrated with Bamboo CI/CD to cut validation effort 60 hrs to 15 hrs and test turnaround 11 days to 4 days, achieving 10 consecutive zero-revision stakeholder sign-offs and resolving all 12 non-conformances plus

Owned Linux IOCTL design and buffer alignment root-cause analysis for MIPI/I2C camera systems, delivering 11 custom IOCTLs and a reusable regression library that standardized integration across engineers. Improved transport-layer performance by fixing IOCTL queuing to remove application blocking, reducing test cycle time from 5 days to 1.5 days and frame latency from 45 ms to 22 ms, alongside cras

Re-engineered SPI/I2C/UART peripheral drivers on embedded platforms, diagnosing silicon-level timing issues and optimizing SPI to 4-byte FIFO burst mode to reduce transfer lag from 2,500 µs to 200 µs (90% improvement). Built CAPA-driven V&V and automated PHY validation pipelines, standardizing scripts and reporting to close the dev-to-verification gap from 10 days to 3 days while freeing 400+ engi

Grade: First Class with Distinction (CGPA 8.04/10)

Completed an MBA in Business Analytics (First Class with Distinction), with CGPA 8.04/10, in Oct 2023.

Completed a B.E. in Electronics and Communication Engineering in Jun 2003.