Open to opportunities

vedant darji

@vedantdarji

Message

Electronics and Communication engineer focused on VLSI design and applied deep learning for computer vision.

India

Message

What I'm looking for

I’m looking for an entry-level role where I can apply VLSI/Verilog design skills and deep learning (CNNs/segmentation) to build robust, testable systems—preferably with strong mentorship and hands-on hardware/software validation.

I’m a B.Tech student in Electronics and Communication Engineering at NITK, building strong foundations across digital electronics, Low power VLSI design, microprocessors, and computer architecture. I enjoy turning ideas into working hardware and models—whether that’s implementing logic in Verilog or training deep learning systems for real-world perception.

Recently, I trained a ResUNet++ model for bacteria image classification using patch-based learning and evaluated it with F1/Dice while studying robustness with and without Fourier Domain Adaptation (FDA). Earlier, as a VLSI Intern, I developed an 8-tap FIR Filter in Verilog with fixed-point arithmetic and validated it through hardware-software co-simulation, and I’ve also built CNN-based handover decision models using transfer learning.

Experience

Work history, roles, and key accomplishments

Summer Intern (ML)

National Institute of Technology Karnataka

Jun 2025 - Aug 2025 (2 months)

Trained a 41-layer ResUNet++ (4M+ trainable parameters) on the DIBaS dataset using patch-based learning to classify bacteria into 4 classes. Evaluated with F1 and Dice scores and achieved 88% accuracy, comparing robustness with and without Fourier Domain Adaptation (FDA).

ResUNet++PyTorch Patch Based Learning DIBaS Dataset F1 Score Dice Coefficient Fourier Domain Adaptation (FDA)

VLSI Intern (Remote)

Codtech IT Solutions

May 2025 - Jul 2025 (2 months)

Developed an 8-tap FIR filter in Verilog using fixed-point arithmetic for real-time hardware-oriented signal processing. Built hardware-software co-simulation by generating inputs in Python and validating outputs via visualization, and designed supporting Verilog modules including SRAM, a pipelined processor, and a basic ALU.

Verilog FIR Filter Design Hardware Simulation Python SRAM Design ALU Design Signal Processing