Tarandeep Kaur
@tarandeepkaur2
Computer Science student building software, web interfaces, and verified hardware systems.
What I'm looking for
I’m a B.Tech in Computer Science and Engineering (IIT Guwahati) focused on building end-to-end systems, from responsive web interfaces to hardware-oriented software. In my course work, I designed and implemented a 5-stage pipelined MIPS in Verilog, developing modular datapath components and validating behavior with testbenches.
I also built an “Automatic Assertion Generator” that uses LLMs to generate temporal logic assertions, then verifies and refines them using nuXmv and counterexamples. Alongside technical projects, I’ve taken leadership roles—running media campaigns for a 50+ member literary society and coordinating events—so I’m comfortable owning execution, communication, and iteration with real feedback.
Experience
Work history, roles, and key accomplishments
Automatic Assertion Generator
Indian Institute Of Technology, Guwahati
Feb 2026 - Present (4 months)
Built a multi-layer pipeline that generates temporal logic assertions from natural-language system descriptions using LLMs. Used multi-model voting, nuXmv model checking with counterexample extraction, and clustering/subsumption to produce minimal assertion sets.
Media Head - Lit-Soc Club
Lit-Soc Club, IIT Guwahati
Mar 2025 - Present (1 year 3 months)
Managed social media campaigns for a 50+ member literary society, increasing post engagement through consistent branding and timely event coverage. Designed promotional content using Canva and Adobe Express and coordinated real-time posting across events.
Developed a comprehensive system to streamline hospital management operations through a centralized platform.
Integrated DB and CRUD operations using backend frameworks and SQL ensuring storage and retrieval of data.
Built responsive frontend interfaces using web technologies to provide smooth navigation and efficient interaction.
Responsive Website
Independent Project
Jun 2025 - Jul 2025 (1 month)
Built a responsive website using HTML, CSS, and JavaScript with cross-device compatible layout and media-query driven styling. Implemented dark/light toggle via CSS custom properties and added scroll reveal animations using ScrollReveal.js.
MIPS Pipelined Verilog
Indian Institute Of Technology, Guwahati
Mar 2025 - Apr 2025 (1 month)
Designed and implemented a 5-stage pipelined MIPS processor in Verilog with modular datapath components and coordinated stage-wise execution using registers. Verified correct pipeline flow and stage interactions with testbenches.
Education
Degrees, certifications, and relevant coursework
Indian Institute of Technology Guwahati
Bachelor of Technology (B.Tech), Computer Science and Engineering
2023 -
Activities and societies: Course/self projects: 5-stage pipelined MIPS in Verilog (Mar 2025–Apr 2025) and an automatic assertion generator using LLMs with nuXmv verification (Feb 2026–present).
Pursuing a B.Tech in Computer Science and Engineering at IIT Guwahati since 2023.
CBSE Board
Senior Secondary Certificate (CBSE)
Completed Senior Secondary education under the CBSE curriculum in 2023.
CBSE Board
Secondary Certificate (CBSE)
Completed Secondary education under the CBSE curriculum in 2021.
Availability
Location
Authorized to work in
Social media
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