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Mayank BhanotMB
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Mayank Bhanot

@mayankbhanot

Senior software engineer at F5 developing Traffic Management Micro-kernel drivers and YANG/NETCONF platform configuration.

United States
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What I'm looking for

I’m targeting senior individual-contributor or lead roles in EU semiconductor, networking, and storage companies. I’m EU Work Permit Eligible through the Blue Card path and calibrated to local-market salary expectations.

At F5, Inc., I’m developing low-level device drivers for the Traffic Management Micro-kernel and implementing YANG data models with NETCONF-based configuration management for platform device interfaces.

At NetApp, I developed C and C++ Linux/FreeBSD kernel components for a next-generation N-way HA interconnect, and created a UUID-based node ID for ONTAP X to support containerized architecture and RDMA consistency.

At AMD, I developed multithreaded C++ linters for the RTL and Verilog design pipeline, improving runtime by 10%. I also created the G2 API and a schema-based system to generate C++ device models from YAML data, and built the Python tool Thrifty, which reduced install image size by 40%.

At Cisco Systems Inc., I developed Embedded Linux software for wireless access point management and implemented DDoS detection and wireless intrusion prevention algorithms. I’m targeting senior individual-contributor or lead roles in EU semiconductor, networking, and storage companies, and am EU Work Permit Eligible through the Blue Card path.

Experience

Work history, roles, and key accomplishments

NetApp logoNE

System Software Engineer

Jan 2025 - Aug 2026 (1 year 7 months)

Developing the next-generation N-way HA interconnect stack using C, C++ and Linux/FreeBSD kernel components, replacing the 1:1 partner model with a dynamic N-node peer-to-peer architecture. Developed UUID-based node ID in C for ONTAP X and debugged high-performance distributed storage architectures with RoCE and NVMe-oF.

AMD logoAM

Sr. Software Engineer

Nov 2021 - Jan 2025 (3 years 2 months)

Designed next-generation device model solutions for newly introduced hardware. Developed C++ based multithreaded linters for efficiency tooling in the RTL and Verilog design pipeline, improving runtime by 10%. Created the G2 API and a schema-based system to auto-generate device models, and developed a tool called Thrifty using Python, reducing install image size by 40%.

Education

Degrees, certifications, and relevant coursework

University of California, Davis logoUD

University of California, Davis

Master of Science, Computer Engineering

2018 - 2020

Master of Science in Computer Engineering from the University of California, Davis, from 2018 to 2020.

SRM Institute of Science and Technology logoST

SRM Institute of Science and Technology

Bachelor of Science, Electrical Engineering

2013 - 2017

Bachelor of Science in Electrical Engineering from SRM Institute of Science and Technology, from 2013 to 2017.

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