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Dasun Pathirage

@dasunpathirage

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I build C++ and FPGA systems for AI inference hardware.

Sri Lanka

Message

I've built C++ mapping tools and simulators for Sagence AI's Analog Inference accelerator chip, automating neural-network deployment and cutting manual mapping effort by about 60%.

I optimise ResNet, YOLOv5, and FCN workloads for constrained hardware, maintain regression tooling, and build reporting, visualisation, and API tools that make validation and integration faster. I've also mentored engineers in parallel computing, HPC, RISC-V, and SystemVerilog.

For Dexon Technologies, I developed SystemVerilog FPGA firmware and data-acquisition pipelines for real-time magnetic sensor logging. My work spans SPI/QSPI controllers, PSRAM integration, low-latency state machines, and verified FPGA designs.

Experience

Work history, roles, and key accomplishments

Current

Senior Consultant Engineer

Current

Sagence AI

Jan 2024 - Present (2 years 8 months)

Served as primary technical point of contact for backend mapper architecture decisions and architected an automated neural network mapping tool in C++ that deploys models onto the Analog Inference data-flow accelerator chip, cutting manual mapping effort by ~60%. Conducted optimisation experiments on ResNet, YOLOv5, and FCN models, achieving measurable improvements in inference throughput and mode

C++Neural Network Mapping ResNet YOLO V5 FCN AI Hardware Accelerators Optimization Technical Leadership Stakeholder Management

FPGA Firmware Engineer

Dexon Technologies

Jan 2024 - Dec 2024 (11 months)

Designed a scalable SystemVerilog external-device controller with SPI/QSPI interface supporting multiple sensors, configurable FIFO buffering, and memory-mapped control/status registers. Developed FPGA firmware for a Magnetic Logging Facility (MLF) data-logger, capturing and buffering real-time magnetic sensor data streams with PSRAM interface integration.

SystemVerilog FPGA SPI QSPI PSRAM Lattice Radiant Questa Data Acquisition State Machines Memory Controller

Senior Software Engineer

Sagence AI

Jan 2020 - Dec 2024 (4 years 11 months)

Led development of the back-end neural network mapper tool (C++) that automatically maps neural network graphs onto the Analog Inference accelerator chip, improving space utilisation through novel mapping policies. Managed the test regression suite of 100+ test cases (Python), cutting regression failures and ensuring tool stability across releases.

C++Python Neural Network Mapping Regression Testing Model Visualization ARM Development Studio YOLO V5 RISC V SystemVerilog Parallel Computing HPC Mentorship

Electronic Engineering Trainee

Paraqum Technologies

Jan 2018 - Dec 2018 (11 months)

Gained hands-on experience in FPGA electronic design and parallel processing within a network-products environment. Developed a Slack messaging bot and a Gmail email verification system in C++ (libcurl), streamlining team communication workflows.