At Celerix Technologies, I rebuilt the market trigger engine for NSE and BSE into a production system delivered to multiple trading clients. Its cut-through pipeline reached 140–143 ns tick-to-trade, and I reduced in-FPGA latency from 124 ns to 106 ns by parallelizing pipeline stages.
I built the pipeline from market-data parsing through trigger evaluation and TCP order generation. I also translated client C++ strategy logic into RTL and implemented configurable triggers for 512 tokens and 1,024 triggers.
For NSE order encryption, I added AES-256-GCM and TAQ ID generation, then redesigned the re-encryption path when the existing core was too slow. That cut re-encryption time from 194 µs to approximately 6 µs.
I also designed a dual-feed synchronizer for NSE, BSE and MCX, and worked on order-book and trigger pipelines. Across projects, I closed timing at 322 MHz, brought designs up on multiple FPGA platforms, and built PCAP-replay verification and a standalone latency-measurement rig.
