At UST Global, I own validation of Hardware Security Processor firmware releases for Microsoft’s Maia 200/300 AI accelerators, from test planning through release sign-off. My work includes validating root-of-trust and SR-IOV isolation, as well as boot, reset, and update flows across pre-silicon platforms and production silicon.
I developed Python and Robot Framework automation for previously manual test cases and integrated it into CI/CD pipelines. I also lead first-level triage and root cause analysis, fixing automation defects, debugging platform issues, and escalating reproduced firmware issues with logs and reproduction steps.
For Intel Xeon server platforms, I planned and executed pre- and post-silicon validation across three generations of processors. I built Python automation and regression pipelines for 300+ test cases, cutting validation cycle time by 60%.
My validation work has covered power and performance, DDR memory, PCIe, and platform bring-up. I’ve used environments including ZeBu, HAPS, QEMU, and production silicon, and debugged issues with JTAG, ITP, and logic analyzers.
