
Kostas Skantzis
@kostasskantzis
PCB and hardware designer.
What I'm looking for
I designed and constructed a photovoltaic I-V curve tracer for modules up to 1.5 kV open-circuit voltage and 15 A short-circuit current. The project brought together custom PCB design, power electronics, embedded systems, software debugging, and PV emulation.
I also designed and constructed a controllable DC electronic load for pulsed and steady-state operation, with current- and voltage-limiting functions for DUT prototyping and laboratory testing.
On the UoP Racing PCB Design Team, I contributed to PCB design and worked under defined design standards with engineers from different technical disciplines. My other hardware designs include a 10 kW full-bridge inverter, a 5 kW four-phase interleaved boost converter, a passive BMS, and a Colpitts oscillator.
For FPGA work, I implemented the CLEFIA cryptographic algorithm using VHDL and Vivado, increasing throughput from a 1.3 Gbps baseline to 32 Gbps through replication and pipelining. I’m an Electrical & Computer Engineer and PhD Candidate focused on PCB and hardware design for power-electronic and high-speed systems.
Experience
Work history, roles, and key accomplishments
Controllable Electronic Load - Active Power Hardware
University of Patras
Apr 2025 - May 2026 (1 year 1 month)
Designed and constructed a controllable DC electronic load for both pulsed and steady-state operation. Implemented current-limiting and voltage-limiting functionality for DUT prototyping and laboratory testing.
Diploma Thesis - Photovoltaic I-V Curve Tracer
University of Patras
Apr 2025 - May 2026 (1 year 1 month)
Designed and constructed a photovoltaic I-V curve tracer for modules up to 1.5 kV open-circuit voltage and 15 A short-circuit current. Worked across power electronics, custom PCB design, embedded systems, software debugging and PV emulation.
CLEFIA Cryptographic Accelerator - FPGA / VHDL
University of Patras
Dec 2025 - Mar 2026 (3 months)
Designed, optimized and implemented the CLEFIA symmetric cryptography algorithm on FPGA using VHDL and Vivado. Achieved 1.3 Gbps baseline throughput and increased throughput to 32 Gbps using architectural replication and pipelining.
High-Speed Local Clock Distribution Network
University of Patras
Dec 2025 - Feb 2026 (2 months)
Designed and simulated an asymmetric clock-distribution network targeting 3.3 GHz, with additional experiments at 10 GHz. Applied skew-minimization techniques and eliminated nominal-condition skew in simulation.
PCB Design Team Contribution
UoP Racing
Oct 2024 - Apr 2025 (6 months)
Contributed to the design of PCBs within a multidisciplinary engineering team. Worked under defined design standards and coordinated with engineers from different technical disciplines.
AI-hub Competition - 1st Place
University of Patras
Mar 2023 - Oct 2023 (7 months)
Developed deep-learning and machine-learning models for predictive maintenance and contributed to input-data analysis and transformation. Project: Smart Data Enabled Maintenance Strategies - A Path to Operational Excellence.
Education
Degrees, certifications, and relevant coursework
University of Patras
Integrated MEng, Electrical & Computer Engineering
2021 - 2026
Grade: 8.6/10
Integrated MEng in Electrical & Computer Engineering with a GPA of 8.6/10, ranking top 5 in class.
Leibniz Universität Hannover
International Summer School of Microelectronics, Microelectronics
2025 - 2025
Five-day program covering the chip lifecycle, high-voltage systems, RF electronics, radar and EDA.
Tech stack
Software and tools used professionally
Availability
Location
Authorized to work in
Salary expectations
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