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Joao CassianoJC
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Joao Cassiano

@joaocassiano

ASIC Digital Design Sr Engineer at Synopsys, working on digital design after developing RISC-V encryption on FPGA.

Portugal
Message

At Synopsys Inc., I work as an ASIC Digital Design, Sr Engineer. I previously worked there as an ASIC Digital Design Engr II and completed the Synopsys Microelectronics Academy - fall edition internship.

For my master's work at Universidade da Beira Interior, I worked on encryption and authentication in a RISC-V architecture, including a RISC-V softcore on an FPGA, ChaCha20-Poly1305, and IEEE 1451.

As co-founder and managing partner of ZennerBox, I was responsible for technological development. I also worked as a lighting technician and stage manager at RM-audiovisuais, where I used and programmed Avolites.

My experience and studies include embedded systems, electronics engineering, and cybersecurity. I also worked as a solar energy technician.

Experience

Work history, roles, and key accomplishments

Synopsys Inc logoSI
Current

ASIC Digital Design, Sr Engineer

Mar 2024 - Present (2 years 7 months)

Worked as ASIC Digital Design, Sr Engineer at Synopsys Inc.

Synopsys Inc logoSI

ASIC Digital Design Engr II

Feb 2024 - Mar 2024 (1 month)

Worked as ASIC Digital Design Engr II at Synopsys Inc.

Synopsys Inc logoSI

Synopsys Microelectronics Academy - fall edition

Nov 2023 - Jan 2024 (2 months)

Worked as Synopsys Microelectronics Academy - fall edition at Synopsys Inc.

RM-audiovisuais logoRM

Lighting technician and stage manager

Jan 2018 - Sep 2023 (5 years 8 months)

Avolites user and programmer

ZennerBox logoZE

Chief Executive Officer

Oct 2020 - Dec 2022 (2 years 2 months)

Co-founder and managing partner of the startup ZennerBox.
Responsible for technological development

Freelance logoFR

solar energy technician

Jul 2017 - Aug 2017 (1 month)

Worked as solar energy technician at Freelance.

Education

Degrees, certifications, and relevant coursework

US

Università degli Studi di Salerno

Engenharia Elétrica e Eletrônica

2023 - 2023

UI

Universidade da Beira Interior

Mestrado, Engenharia Eletrotécnica e de Computadores

2020 - 2023

"Encryption and authentication in a RISC-V architecture":
Risc-v softcore on a FPGA
Chaca20-Poly1305
IEEE1451

Tech stack

Software and tools used professionally

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