Looking for a job

Asaf Zini

@asafzini

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I build RTL-to-GDS ASICs and FPGA systems, with hands-on digital verification and timing closure experience.

Israel

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What I'm looking for

I'm seeking a chip design or digital verification position where I can apply RTL-to-GDS ASIC, FPGA, timing closure, and verification experience.

I've built a complete RISC-V SoC from RTL to GDS, including CPU, memory, UART communication, and real firmware execution. I achieved 50MHz timing closure on a 130nm ASIC flow with a 100% test pass rate.

I'm a fourth-year Electrical Engineering and Physics student at Tel Aviv University, focused on RTL design, ASIC implementation, FPGA systems, and digital verification. My work also includes FPGA game hardware, medical-imaging ML infrastructure, and maintaining mission-critical FPGA-based systems in operational environments.

Experience

Work history, roles, and key accomplishments

Hardware Operations Engineer Coordinator

MGAR Group

Jan 2022 - Dec 2023 (1 year 11 months)

Maintained and optimized hardware infrastructure for 50+ users, ensuring high availability in production environments.

Hardware Infrastructure High Availability Production Systems

Air Defense Intelligence Communication Specialist

Israeli Air Forces

Jan 2020 - Dec 2022 (2 years 11 months)

Maintained and debugged mission-critical FPGA-based systems in operational environments, resolving signal integrity issues on high-speed interfaces and achieving 80% latency reduction across distributed sites.

FPGA Signal Integrity Debugging