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@0009076

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Analog and mixed-signal IC layout engineer at Intel/Altera who taped out a 112G SerDes transmitter PISO on TSMC N5.

Israel

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At Intel Corporation / Altera, I designed full-custom, transistor-level layouts for high-speed SerDes IPs on advanced FinFET nodes. I owned block-level layouts from device matching through parasitic-aware optimization.

I ran DRC, LVS, and RV with Calibre, and EM/IR analysis with Totem. I resolved violations and implemented ECOs through tape-out.

I was selected for the TSMC N3 ramp-up and led knowledge transfer to layout teams in the US and Malaysia. I also mentored 4 layout engineers through guidance and layout reviews.

For the 112G SerDes Transmitter PISO on TSMC N5, I completed full-custom layout under tight area constraints, and it taped out successfully. Other projects included an Intel 18A LDO block that reached clean physical verification and high-frequency dividers on TSMC N5.

Experience

Work history, roles, and key accomplishments

Current

Reserve Duty, Combat Support

Current

IDF

Jan 2025 - Present (1 year 10 months)

Extended periods of active reserve service.

Analog Layout Design Engineer

Intel Corporation

Jan 2018 - Dec 2025 (7 years 11 months)

Designed full-custom transistor-level layouts for high-speed SerDes IPs on advanced FinFET nodes, owning block-level layouts end to end. Ran physical verification (DRC, LVS, RV) with Calibre and EM/IR analysis with Totem, resolving violations and implementing ECOs under tape-out schedules.