Silicon Packaging Substrate Design Engineer

Responsibilities

• As a Packaging substrate designer, you will own or participate in the following:
• Work with cross-functional teams to select the optimized package solution
• Work with IC design, system design, SIPI, thermal, and mechanical engineering teams to design custom substrates and interposers.
• Work with SoC design teams to optimize die floorplan, bump patterns, and interposer/substrate stackup.
• Own substrate design deliverables at critical design checkpoints and release substrate to vendors for manufacturing.
• Responsible for POD and related technical documentation for the package.
• Work with overseas assembly partners for product bring-up, qualification, and ramp to HVM.

Requirements

• Experience in substrate layouts and design in advanced package technologies.
• Experience or knowledge of2.5D, and 3D package substrate and interposer design.
• Experience with design teams on floor plan, bump, and layout optimization.
• Strong authority on Cadence Allegro Package Designer (APD).
• Excellent problem-solving, written and verbal communication skills, and organization skills. Self-motivated.
• Ability to work well in a team and be productive under aggressive schedules.

Education and Experience

• PhD, Master's, or BS Degree with 7+ years of experience in the subject area.