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@ms019

Physical Design Engineer at TSMC implementing advanced-node SoCs at 2 nm and 3 nm.

Japan
Message

At TSMC, I work on block-level implementation of advanced-node SoCs at the 2 nm and 3 nm technology nodes.

My work includes Place & Route, timing closure, physical signoff, ECO implementation, and tapeout. I use Cadence Innovus, Synopsys PrimeTime, Cadence Voltus, and Calibre, and enjoy developing practical solutions to implementation challenges.

Experience

Work history, roles, and key accomplishments

TSMC logoTS
Current

Physical Design Engineer

Apr 2024 - Present (2 years 6 months)

Physical design engineer

ROHM Co., Ltd. logoRL

Reliability Engineer

Apr 2023 - Mar 2024 (11 months)

Worked as Reliability Engineer at ROHM Co., Ltd..

Education

Degrees, certifications, and relevant coursework

OU

Osaka Metropolitan University

Master's degree, Electrical and Electronics Engineering

2019 - 2023

Tech stack

Software and tools used professionally

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