Open to opportunities

Khaled Amarneh

@khaledamarneh

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Aspiring computer engineer with a passion for full stack development.

Palestine, State of

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What I'm looking for

I am looking for a collaborative environment that fosters growth and innovation.

I am a motivated computer engineer with a Bachelor's degree from Birzeit University, where I honed my skills in design verification and programming. My journey began with designing an ALU using Verilog and progressed to creating complex UVM components, showcasing my ability to tackle challenging problems with innovative solutions.

Currently, I am a Design Verification Trainee at ASAL Technologies and have gained valuable experience as a Full Stack Developer at Universe and AppiaTech. I excel in developing web applications using .NET, Angular, and SQL, while applying Agile methodologies to ensure high-quality deliverables. My projects include building a movie recommendation system that utilizes graph neural networks, demonstrating my commitment to leveraging cutting-edge technology.

Experience

Work history, roles, and key accomplishments

Current

Full Stack Developer

Current

Universe

Jul 2023 - Present (1 year 11 months)

Developed and designed web applications using .NET 6, C#, SQL Server, and Angular. Applied Agile/SCRUM methodologies to deliver scalable solutions and optimized performance through multi-threading.

C++SQL Server Angular Agile Scrum

Full Stack Developer

AppiaTech

Jul 2021 - Feb 2023 (1 year 7 months)

Developed web applications using .NET framework, C#, and Angular. Enhanced backend performance and performed extensive testing to ensure high code coverage and reliability.

.NET Framework C++Angular SQL Server Unit Testing

Design Verification Trainee

ASAL Technologies

Aug 2020 - Sep 2020 (1 month)

Worked on designing an ALU and UVM components using Verilog and System Verilog. Developed testbenches and wrote a test plan for UVM memory, enhancing skills in digital design and verification.

Verilog Digital Design

Education

Degrees, certifications, and relevant coursework

Birzeit University

Bachelor's Degree, Computer Engineering

2016 - 2021

Designed an ALU with a testbench using Verilog language. Developed a UVM full adder and UVM memory with their testbenches using System Verilog. Wrote a test plan for a UVM memory.