At ChipMango Limited, I led a four-person team delivering an AES-128/SHA-256 cryptography coprocessor for an NFC-based voter system. I designed both datapaths in SystemVerilog and verified them against Python golden models and NIST FIPS vectors.
I kept one RTL codebase running on Xilinx Artix-7 and Altera Cyclone hardware, resolving differences in clocking, constraints, and memory inference. We demonstrated both datapaths working on a Basys 3 board.
On HashPareto, I explored SHA-256 design tradeoffs from RTL through SKY130 GDSII, using cocotb verification and PPA analysis. I also contributed SoC integration, a custom AXI4-Lite GPU peripheral, and C driver and game logic to TeenyTiny GPU.
