At the Institute of Computing Technology, Chinese Academy of Sciences, I modified and validated a SystemC NoC model. I used trace and waveform analysis to confirm packet generation, routing, and reception.
I compared network configurations under controlled traffic, routing, and buffering conditions to distinguish topology-dependent from load-dependent performance. I also analyzed how bottlenecks shifted across workloads, operating areas, and load levels.
At Beijing Open Source Chip Research Institute, I developed and debugged a RISC-V boot chain on QEMU. I resolved a BusyBox /init failure by cross-checking logs, the rootfs, Device Tree, and MMIO mappings.
I also debugged hvisor hypervisor and guest communication, validating interrupt delivery and multicore memory behavior. I improved the rootfs, DTS, and kernel-image generation workflow with staged checkpoints and regression checks.
