# Hire the best remote VLSI Engineer employees

Discover 169 remote VLSI Engineer workers who are looking for their next full-time, part-time or freelance opportunity on Himalayas.

Source: https://himalayas.app/talent/vlsi-engineer

## 169 remote workers

| Person | Role | Location | Salary expectations | Intro |
| --- | --- | --- | --- | --- |
| [SADU NITEESH](https://himalayas.app/@saduniteesh) | VLSI Engineer | India |  | I'm a VLSI physical design engineer focused on RTL-to-GDSII implementation, timing analysis, and block-level PnR. |
| [Rubeena Tarannum](https://himalayas.app/@rubeenatarannum) | VLSI Engineering | India |  | VLSI design and verification trainee focused on reliable, standards-compliant IC development. |
| [Sathvika Lakkasandram](https://himalayas.app/@sathvikalakkasandram) | VLSI Engineer | India |  | I design and verify VLSI RTL, protocol bridges, and digital systems using Verilog and SystemVerilog. |
| [Neshitha Nichanametla](https://himalayas.app/@neshithanichanametla) | VLSI Engineer | India |  | I build Verilog RISC-V processors and SoC subsystems through RTL-to-GDSII VLSI flows. |
| [Prajyot Patil](https://himalayas.app/@prajyotpatil) | VLSI Design Intern | India |  | Electronics engineer specializing in VLSI design, verification, and CADENCE workflows. |
| [JAHNAVI MUDILI](https://himalayas.app/@jahnavimudili) | Physical Design Engineer | India |  | I'm building VLSI physical design skills through RTL-to-GDSII, synthesis, floorplanning, and timing optimization. |
| [Sakshi Katti](https://himalayas.app/@sakshikatti1) | VLSI Engineer | India | 785k+ INR | VLSI Design trainee at Quantumclk Academy, designing and simulating CMOS logic gates in Cadence Virtuoso. |
| [B Keerthi](https://himalayas.app/@bkeerthi) | VLSI Engineer | India |  | I build digital electronics and VLSI solutions using Verilog, SystemVerilog, and Python. |
| [mohan krishna](https://himalayas.app/@mohankrishna6) | VLSI Engineer | India | 118k+ INR | I build and verify Verilog RTL projects, including a RISC-V core, across VLSI and embedded systems. |
| [Astitva Sharma](https://himalayas.app/@astitvasharma) | VLSI Design Intern | India |  | VLSI engineer specializing in RTL design, verification, and FPGA/ASIC flows. |
| [Vidhi Radhanpura](https://himalayas.app/@vidhiradhanpura) | Verification Engineer | India |  | Verification engineer specializing in VLSI design and UVM-based functional verification with RTL expertise. |
| [R A Bhargavi Mallur](https://himalayas.app/@rabhargavimallur) | Fpga Engineer | India |  | Anticipated Electronics & Communication graduate focused on VLSI front-end design and embedded systems. |
| [Nishchay kumar M](https://himalayas.app/@nishchaykumarm) | ASIC Physical Design Engineer | India | 70k+ INR | VLSI Physical Design fresher trained at VLSI First Training Institute who achieved timing closure on ORCA and ChipTop Processor. |
| [Jitin Naik](https://himalayas.app/@jitinnaik) | VLSI Design Intern | India |  | Entry-level VLSI and embedded systems professional focused on Verilog, ESP32, and real-world electronics. |
| [Mohammed Muneeb](https://himalayas.app/@mohammedmuneeb) | Physical Design Engineer | India |  | VLSI Physical Design engineer focused on timing closure, congestion mitigation, and ASIC/SoC implementation. |
| [Taraseelam Yaswanth](https://himalayas.app/@taraseelamyaswanth) | VLSI Design Intern | India |  | Fresh electronics engineer eager to tackle challenges in VLSI design. |
| [Sree kaushik User](https://himalayas.app/@sreekaushikuser) | VLSI Engineer | India | 1981k+ INR | I build embedded IoT systems and VLSI designs for intelligent, hardware-efficient applications. |
| [Keerthi Sree](https://himalayas.app/@keerthisree) | Physical Design Engineer | India |  | VLSI Physical Design Engineer skilled in 28nm PNR flows. |
| [Swati Kouthankar](https://himalayas.app/@swatikouthankar) | VLSI Engineer | India |  | I'm an electronics engineering graduate building CMOS layouts, embedded healthcare devices, and machine-learning classification systems. |
| [Battinapati Durga Manohar](https://himalayas.app/@battinapatidurgamano) | Verification Engineer | India |  | VLSI verification engineer skilled in SystemVerilog/UVM, delivering robust RTL and coverage-driven verification. |

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To contact someone, message them from their profile with a Himalayas employer account: [Hire on Himalayas](https://himalayas.app/hire).