# Hire the best remote VLSI Design Intern employees

Discover 138 remote VLSI Design Intern workers who are looking for their next full-time, part-time or freelance opportunity on Himalayas.

Source: https://himalayas.app/talent/vlsi-design-intern

## 138 remote workers

| Person | Role | Location | Salary expectations | Intro |
| --- | --- | --- | --- | --- |
| [Jitin Naik](https://himalayas.app/@jitinnaik) | VLSI Design Intern | India |  | Entry-level VLSI and embedded systems professional focused on Verilog, ESP32, and real-world electronics. |
| [Prajyot Patil](https://himalayas.app/@prajyotpatil) | VLSI Design Intern | India |  | Electronics engineer specializing in VLSI design, verification, and CADENCE workflows. |
| [Taraseelam Yaswanth](https://himalayas.app/@taraseelamyaswanth) | VLSI Design Intern | India |  | Fresh electronics engineer eager to tackle challenges in VLSI design. |
| [Sakshi Galle](https://himalayas.app/@sakshigalle) | VLSI Engineer | India | 140k+ INR | VLSI Research Intern at IIIT Dharwad simulating semiconductor devices with Synopsys Sentaurus TCAD in Linux. |
| [JAHNAVI MUDILI](https://himalayas.app/@jahnavimudili) | Physical Design Engineer | India |  | I'm building VLSI physical design skills through RTL-to-GDSII, synthesis, floorplanning, and timing optimization. |
| [vedant darji](https://himalayas.app/@vedantdarji) | VLSI Design Intern | India |  | Electronics and Communication engineer focused on VLSI design and applied deep learning for computer vision. |
| [B Keerthi](https://himalayas.app/@bkeerthi) | VLSI Engineer | India |  | I build digital electronics and VLSI solutions using Verilog, SystemVerilog, and Python. |
| [Neshitha Nichanametla](https://himalayas.app/@neshithanichanametla) | VLSI Engineer | India |  | I build Verilog RISC-V processors and SoC subsystems through RTL-to-GDSII VLSI flows. |
| [Swati Kouthankar](https://himalayas.app/@swatikouthankar) | VLSI Engineer | India |  | I'm an electronics engineering graduate building CMOS layouts, embedded healthcare devices, and machine-learning classification systems. |
| [Likhith Kulal](https://himalayas.app/@likhithkulal) | VLSI Engineer | India | 140k+ INR | I design and verify digital electronics projects, from UART controllers to image encryption systems. |
| [Saravana Rajagobal](https://himalayas.app/@saravanarajagobal) | VLSI Design Intern | Malaysia |  | Computer & Communication Systems engineer specializing in semiconductor validation and VLSI. |
| [mohan krishna](https://himalayas.app/@mohankrishna6) | VLSI Engineer | India | 118k+ INR | I build and verify Verilog RTL projects, including a RISC-V core, across VLSI and embedded systems. |
| [Astitva Sharma](https://himalayas.app/@astitvasharma) | VLSI Design Intern | India |  | VLSI engineer specializing in RTL design, verification, and FPGA/ASIC flows. |
| [Korrapolu Eswar Adithya](https://himalayas.app/@korrapolueswaradithy) | Design Verification Engineer | India |  | I’m an aspiring VLSI RTL design and verification engineer building ASIC/FPGA-ready modules, testbenches, and SVA-driven validation. |
| [RATNA SEETHAL SARIPALLI](https://himalayas.app/@ratnaseethalsaripall) | Electronics Engineer | India | 140k+ INR | I'm an electronics engineering student building VLSI, embedded, and Arduino-based hardware systems. |
| [Sakshi Katti](https://himalayas.app/@sakshikatti1) | VLSI Engineer | India | 785k+ INR | VLSI Design trainee at Quantumclk Academy, designing and simulating CMOS logic gates in Cadence Virtuoso. |
| [Mohammed Muneeb](https://himalayas.app/@mohammedmuneeb) | Physical Design Engineer | India |  | VLSI Physical Design engineer focused on timing closure, congestion mitigation, and ASIC/SoC implementation. |
| [Bhuvan Raj](https://himalayas.app/@bhuvanraj) | VLSI Engineer | India | 2500k+ INR | VLSI Engineer Intern at JSA LAABS integrating an SNN IP on Zynq-7000 and validating hardware against PyTorch models. |
| [Tejomurthula Karthikeya Sarma](https://himalayas.app/@tejomurthulakarthike) | ASIC Physical Design Engineer | India | 300k-400k INR | Graduate in Electronics and Communication Engineering at Raghu Institute Of Technology. Interested in VLSI Physical Design and concepts of it. |
| [SADU NITEESH](https://himalayas.app/@saduniteesh) | VLSI Engineer | India |  | I'm a VLSI physical design engineer focused on RTL-to-GDSII implementation, timing analysis, and block-level PnR. |

Page 1 of 7. Next page: [page 2](https://himalayas.app/talent/vlsi-design-intern.md?page=2)

To contact someone, message them from their profile with a Himalayas employer account: [Hire on Himalayas](https://himalayas.app/hire).