# Hire the best remote VerilogEval employees

Discover 29 remote VerilogEval workers who are looking for their next full-time, part-time or freelance opportunity on Himalayas.

Source: https://himalayas.app/talent/verilogeval

## 29 remote workers

| Person | Role | Location | Salary expectations | Intro |
| --- | --- | --- | --- | --- |
| [Andrew Chen](https://himalayas.app/@andrewchen4) | Fpga Engineer | United States |  | Senior FPGA/ASIC verification engineer specializing in UVM, constrained-random, coverage-driven closure, and high-speed protocol validation. |
| [Battinapati Durga Manohar](https://himalayas.app/@battinapatidurgamano) | Verification Engineer | India |  | VLSI verification engineer skilled in SystemVerilog/UVM, delivering robust RTL and coverage-driven verification. |
| [Vidhi Radhanpura](https://himalayas.app/@vidhiradhanpura) | Verification Engineer | India |  | Verification engineer specializing in VLSI design and UVM-based functional verification with RTL expertise. |
| [sayeekumar swaminathan](https://himalayas.app/@sayeekumarswaminatha) | RTL Design Engineer | India | 200k+ USD | I build and verify RTL processors, microarchitecture, and hardware test suites. |
| [Nithu User](https://himalayas.app/@nithuuser) | Verification Engineer | India |  | Electronics/ECE graduate specializing in SystemVerilog UVM functional verification. |
| [Alejandro García Osés](https://himalayas.app/@alejandrogarcaoss) | Machine Learning Engineer | Spain | 50k+ EUR | Principal Machine Learning Engineer at BrioAI building private legal document intelligence with locally run LLMs and source-validated citations. |
| [Rajesh Valipi](https://himalayas.app/@rajeshvalipi) | Design Verification Engineer | India |  | I’m a Design Verification Engineer specializing in UVM SystemVerilog protocol and VIP development. |
| [Aditya Raut](https://himalayas.app/@adityaraut3) | Design Verification Engineer | India |  | I design and verify FPGA-based digital interfaces and high-speed arithmetic RTL. |
| [Mahendar Mahi](https://himalayas.app/@mahendarmahi) | Verification Engineer | India |  | VLSI verification engineer specializing in UVM and protocol verification. |
| [Keshava jaya ram Chitturi](https://himalayas.app/@keshavajayaramchittu) | Verification Engineer | India |  | Verification engineer specializing in UVM verification, FPGA validation, and debugging for camera ISP and AI accelerators. |
| [Faisal Saeed Awan](https://himalayas.app/@faisalsaeedawan) | Verification Engineer | Pakistan |  | I’m a UVM ASIC/SoC Functional Verification Engineer focused on first-pass silicon. |
| [Nitu Kumari](https://himalayas.app/@nitukumari) | Senior Verification Engineer | India |  | Experienced ASIC Verification Engineer specializing in pre-silicon validation. |
| [Aishwarya Subramanian](https://himalayas.app/@aishwaryasubramanian) | Senior Verification Engineer | India |  | Skilled design verification engineer focused on optimizing testbench performance. |
| [Lavanya-G4 Vlsi User](https://himalayas.app/@lavanya-g4vlsiuser) | Verification Engineer | India |  | Aspiring Design Verification Engineer experienced in Verilog, SystemVerilog and RTL verification. |
| [Ali Sajjad](https://himalayas.app/@alisajjad-dev) | Verification Engineer | Pakistan |  | RTL Design and Formal Verification engineer specializing in RISC-V and floating-point units. |
| [Sindhu G](https://himalayas.app/@sindhug1) | Design Verification Engineer | United States | 60k+ USD | Graduate Verification Engineer at Arm executing CPU/SoC regressions and debugging SystemVerilog/UVM verification failures. |
| [Krishnam Shastri](https://himalayas.app/@krishnamshastri) | Design Verification Engineer | India | 1490k+ INR | Design Verification Engineer at NXP Semiconductors who achieved formal sign-off for multiple RTL blocks across SoCs. |
| [Tehrim k](https://himalayas.app/@tehrimk) | Design Verification Engineer | India | 650k+ INR | I build UVM verification environments for AMBA protocols and RTL designs. |
| [Aman K](https://himalayas.app/@amank1) | Asic Verification Engineer | India |  | SoC/IP verification engineer specializing in SV/UVM, protocol VIPs, and debug automation. |
| [Ganesh Gorli](https://himalayas.app/@ganeshgorli) | Asic Verification Engineer | United States |  | I build and verify FPGA and ASIC systems for AI computing. |

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To contact someone, message them from their profile with a Himalayas employer account: [Hire on Himalayas](https://himalayas.app/hire).