# Hire the best remote Verilog employees

Discover 153 remote Verilog workers who are looking for their next full-time, part-time or freelance opportunity on Himalayas.

Source: https://himalayas.app/talent/verilog

## 153 remote workers

| Person | Role | Location | Salary expectations | Intro |
| --- | --- | --- | --- | --- |
| [Aditya Raut](https://himalayas.app/@adityaraut3) | Design Verification Engineer | India |  | I design and verify FPGA-based digital interfaces and high-speed arithmetic RTL. |
| [Ponnitivalasa Manikantha](https://himalayas.app/@ponnitivalasamanikan) | RTL Design Engineer | India | 1259k+ INR | Aspiring RTL Design Engineer focused on VLSI, who optimized RTL timing and designed RISC-V processors. |
| [Rubeena Tarannum](https://himalayas.app/@rubeenatarannum) | VLSI Engineering | India |  | VLSI design and verification trainee focused on reliable, standards-compliant IC development. |
| [Tehrim k](https://himalayas.app/@tehrimk) | Design Verification Engineer | India | 650k+ INR | I build UVM verification environments for AMBA protocols and RTL designs. |
| [NagendraReddy User](https://himalayas.app/@nagendrareddyuser1) | Design Verification Engineer | India | 30k+ USD | Design Verification Engineer focused on SystemVerilog and UVM, with an AXI4 verification environment covering all five channels. |
| [Vidhi Radhanpura](https://himalayas.app/@vidhiradhanpura) | Verification Engineer | India |  | Verification engineer specializing in VLSI design and UVM-based functional verification with RTL expertise. |
| [Lavanya-G4 Vlsi User](https://himalayas.app/@lavanya-g4vlsiuser) | Verification Engineer | India |  | Aspiring Design Verification Engineer experienced in Verilog, SystemVerilog and RTL verification. |
| [Dousik Manokaran](https://himalayas.app/@dousikmanokaran) | RTL Design Engineer | India | 632k+ INR | I build pipelined RISC-V processors and RTL hardware blocks for efficient digital systems. |
| [Preetham YG](https://himalayas.app/@preethamyg) | VLSI Engineer | India | 70k+ INR | VLSI Design Verification Trainee at ChipEdge who verified APB and AXI protocols using SystemVerilog and UVM. |
| [Valsa Shiva](https://himalayas.app/@valsashiva) | RTL Design Engineer | India | 140k+ INR | RTL design engineer building Verilog/SystemVerilog modules and a 5-stage RISC-V processor for FPGA. |
| [Chitrangi Kasliwal](https://himalayas.app/@chitrangikasliwal) | VLSI Engineer | India | 70k+ INR | VLSI research intern at Advanced VLSI Laboratory, IET, DAVV who translated a MATLAB JPEG prototype into a 14-module Verilog codec. |
| [Bala Venkateswara Gupta](https://himalayas.app/@balavenkateswaragupt) | Design Verification Engineer | India | 2500k+ INR | Design Verification Engineer at Soctronics, verifying AMD Audio IP across two SoC programs and validating low-power behavior. |
| [Chirag Dalsaniya](https://himalayas.app/@chiragdalsaniya) | Asic Verification Engineer | India | 1058k+ INR | I build and verify RTL designs using Verilog, SystemVerilog, UVM, and coverage-driven verification. |
| [vahram sim](https://himalayas.app/@vahramsim) | FPGA Design Engineer | Armenia |  | Junior FPGA design engineer specializing in RTL, verification, and board bring-up. |
| [Sakshi Galle](https://himalayas.app/@sakshigalle) | VLSI Engineer | India | 140k+ INR | VLSI Research Intern at IIIT Dharwad simulating semiconductor devices with Synopsys Sentaurus TCAD in Linux. |
| [SAIPRASAD ARALE](https://himalayas.app/@saiprasadarale) | Design Verification Engineer | India | 140k+ INR | Embedded systems and design verification engineer developing Verilog adder architectures and Arduino-based automation projects. |
| [Korrapolu Eswar Adithya](https://himalayas.app/@korrapolueswaradithy) | Design Verification Engineer | India |  | I’m an aspiring VLSI RTL design and verification engineer building ASIC/FPGA-ready modules, testbenches, and SVA-driven validation. |
| [Mahendar Mahi](https://himalayas.app/@mahendarmahi) | Verification Engineer | India |  | VLSI verification engineer specializing in UVM and protocol verification. |
| [Jitin Naik](https://himalayas.app/@jitinnaik) | VLSI Design Intern | India |  | Entry-level VLSI and embedded systems professional focused on Verilog, ESP32, and real-world electronics. |
| [Pragati Piragannavar](https://himalayas.app/@pragatipiragannavar) | ASIC and SoC Design Engineer | India | 6949k+ INR | ASIC and SoC design verification engineer who verified an AXI4-Lite slave and built RTL projects including a RISC-V RV32I processor. |

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To contact someone, message them from their profile with a Himalayas employer account: [Hire on Himalayas](https://himalayas.app/hire).