# Hire the best remote UVM Testbench Engineer employees

Discover 37 remote UVM Testbench Engineer workers who are looking for their next full-time, part-time or freelance opportunity on Himalayas.

Source: https://himalayas.app/talent/uvm-testbench-engineer

## 37 remote workers

| Person | Role | Location | Salary expectations | Intro |
| --- | --- | --- | --- | --- |
| [Nithu User](https://himalayas.app/@nithuuser) | Verification Engineer | India |  | Electronics/ECE graduate specializing in SystemVerilog UVM functional verification. |
| [Nikita Agrawal](https://himalayas.app/@nikitaagrawal) | Design Verification Engineer | India | 1538k+ INR | Design Verification Engineer who developed UVM testbench components at Intel and built a Python-based UVM framework generator. |
| [Tehrim k](https://himalayas.app/@tehrimk) | Design Verification Engineer | India | 650k+ INR | I build UVM verification environments for AMBA protocols and RTL designs. |
| [Mahendar Mahi](https://himalayas.app/@mahendarmahi) | Verification Engineer | India |  | VLSI verification engineer specializing in UVM and protocol verification. |
| [Faisal Saeed Awan](https://himalayas.app/@faisalsaeedawan) | Verification Engineer | Pakistan |  | I’m a UVM ASIC/SoC Functional Verification Engineer focused on first-pass silicon. |
| [Vidhi Radhanpura](https://himalayas.app/@vidhiradhanpura) | Verification Engineer | India |  | Verification engineer specializing in VLSI design and UVM-based functional verification with RTL expertise. |
| [Rajesh Valipi](https://himalayas.app/@rajeshvalipi) | Design Verification Engineer | India |  | I’m a Design Verification Engineer specializing in UVM SystemVerilog protocol and VIP development. |
| [Akhilesh Ibrahimpet](https://himalayas.app/@akhileshibrahimpet) | Design Verification Engineer | India |  | I build SystemVerilog/UVM verification environments for RTL, memory controllers, and AMBA protocol designs. |
| [Twaheer N](https://himalayas.app/@twaheern) | Design Verification Engineer | India | 140k+ INR | Design Verification Engineer at Saksham Semiconductors who developed RTL for 5+ IP blocks and achieved 98% functional coverage with a UVM testbench. |
| [Hithaishi S R](https://himalayas.app/@hithaishisr) | Design Verification Engineer | India | 70k+ INR | Design Verification Engineer at Aura Semiconductor verifying mixed-signal Smart Power Stage ICs and supporting tape-outs. |
| [Battinapati Durga Manohar](https://himalayas.app/@battinapatidurgamano) | Verification Engineer | India |  | VLSI verification engineer skilled in SystemVerilog/UVM, delivering robust RTL and coverage-driven verification. |
| [Srikanta S M](https://himalayas.app/@srikantasm) | Design Verification Engineer | India | 300k+ INR | Staff Verification Engineer at Krutrim verifying IEEE 754 floating-point IP for an AI accelerator chiplet using SystemVerilog and UVM. |
| [Keshava jaya ram Chitturi](https://himalayas.app/@keshavajayaramchittu) | Verification Engineer | India |  | Verification engineer specializing in UVM verification, FPGA validation, and debugging for camera ISP and AI accelerators. |
| [Preetham YG](https://himalayas.app/@preethamyg) | VLSI Engineer | India | 70k+ INR | VLSI Design Verification Trainee at ChipEdge who verified APB and AXI protocols using SystemVerilog and UVM. |
| [NagendraReddy User](https://himalayas.app/@nagendrareddyuser1) | Design Verification Engineer | India | 30k+ USD | Design Verification Engineer focused on SystemVerilog and UVM, with an AXI4 verification environment covering all five channels. |
| [Bhanu Naga Sarika Neelam](https://himalayas.app/@bhanunagasarikaneela) | Verification Engineer | India |  | RTL verification engineer focused on UVM-based functional coverage for ASIC/SoC. |
| [Andrew Chen](https://himalayas.app/@andrewchen4) | Fpga Engineer | United States |  | Senior FPGA/ASIC verification engineer specializing in UVM, constrained-random, coverage-driven closure, and high-speed protocol validation. |
| [Bhavana Medepalli](https://himalayas.app/@bhavanamedepalli) | Design Verification Engineer | India | 84k+ USD | Design Verification Engineer at AionSi verifying UFS device operations and automating regression triage with Python. |
| [AARTI PRAJAPATI](https://himalayas.app/@aartiprajapati) | Design Verification Engineer | India | 80k+ INR | Design Verification Engineer at Electronics Corporation of India Limited, verifying AXI4-to-AHB-Lite bridges with SystemVerilog and UVM. |
| [PRANUTHI POLIPOGU](https://himalayas.app/@pranuthipolipogu) | ASIC FPGA Engineer | India | 70k+ INR | ASIC/FPGA Design Engineer who developed an AXI-to-AHB bridge and reusable UVM testbench for protocol verification. |

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