# Hire the best remote SoC Design Engineer employees

Discover 48 remote SoC Design Engineer workers who are looking for their next full-time, part-time or freelance opportunity on Himalayas.

Source: https://himalayas.app/talent/soc-design-engineer

## 48 remote workers

| Person | Role | Location | Salary expectations | Intro |
| --- | --- | --- | --- | --- |
| [Pallavi Das](https://himalayas.app/@pallavidas2) | SoC Design Engineer | India |  | I build SoC physical design and timing closure flows from RTL to signoff. |
| [Pragati Piragannavar](https://himalayas.app/@pragatipiragannavar) | ASIC and SoC Design Engineer | India | 6949k+ INR | ASIC and SoC design verification engineer who verified an AXI4-Lite slave and built RTL projects including a RISC-V RV32I processor. |
| [Sathvika Lakkasandram](https://himalayas.app/@sathvikalakkasandram) | VLSI Engineer | India |  | I design and verify VLSI RTL, protocol bridges, and digital systems using Verilog and SystemVerilog. |
| [Ritesh Jadhav](https://himalayas.app/@riteshjadhav2) | RTL Design Engineer | India | 70k+ INR | RTL design engineer at Accenture who developed DMA, I3C, and SHA IPs and implemented I3C protocol features. |
| [veda s](https://himalayas.app/@vedas) | ASIC Design Engineer | India |  | RTL/ASIC Design Engineer specializing in RTL quality, CDC sign-off, and SoC integration. |
| [Foez Ahmed](https://himalayas.app/@foezahmed) | RTL Design and Verification Engineer | Bangladesh | 30k+ USD | Lead RTL Design & Verification Engineer at ADN Semiconductors, defining DDR controller microarchitecture and AXI integration. |
| [nikhitha annthomas](https://himalayas.app/@nikhithaannthomas) | Physical Design Engineer | India |  | VLSI Physical Design Engineer delivering RTL-to-GDSII timing, PnR, and power-optimized SoCs. |
| [RAVINDRA SINGH](https://himalayas.app/@ravindrasingh6) | Design Verification Engineer | Ireland | 90k+ EUR | IP/SoC design verification consultant at Logixchip Technologies, verifying AI compute SoCs and die-to-die interconnects. |
| [Thanasis Karachalios](https://himalayas.app/@thanasiskarachalios) | Silicon Design Engineer | Greece |  | I architect complex semiconductor SoCs and wireless baseband accelerators. |
| [M S](https://himalayas.app/@ms019) | Physical Design Engineer | Japan | 2580k+ JPY | Physical Design Engineer at TSMC implementing advanced-node SoCs at 2 nm and 3 nm. |
| [Bala Venkateswara Gupta](https://himalayas.app/@balavenkateswaragupt) | Design Verification Engineer | India | 2500k+ INR | Design Verification Engineer at Soctronics, verifying AMD Audio IP across two SoC programs and validating low-power behavior. |
| [Neshitha Nichanametla](https://himalayas.app/@neshithanichanametla) | VLSI Engineer | India |  | I build Verilog RISC-V processors and SoC subsystems through RTL-to-GDSII VLSI flows. |
| [Eneraldo Del](https://himalayas.app/@eneraldodel) | SoC Verification Engineering | Greece | 62k+ EUR | SoC Verification Engineer at Capgemini Engineering, working on SoC verification after design verification at HDL Design House. |
| [Rohit Garg](https://himalayas.app/@rohitgarg2) | SoC Performance Modeling Engineer | India | 3737k+ INR | I build SoC performance models that uncover bandwidth and latency bottlenecks. |
| [Ravindra Singh](https://himalayas.app/@ravindrasingh2) | Design Verification Engineer | Ireland |  | I build UVM testbenches and formal verification solutions for complex IP, subsystems, and SoCs. |
| [Deepan Kumaar User](https://himalayas.app/@deepankumaaruser) | Chip Software Engineer | Finland |  | I build and prototype RISC-V SoCs, FPGA systems, and hardware accelerators. |
| [Srikanta S M](https://himalayas.app/@srikantasm) | Design Verification Engineer | India | 300k+ INR | Staff Verification Engineer at Krutrim verifying IEEE 754 floating-point IP for an AI accelerator chiplet using SystemVerilog and UVM. |
| [Nameer Iqbal Ansari](https://himalayas.app/@nameeriqbalansari) | Digital Designer | Pakistan |  | Digital Design Engineer specializing in SoC architecture and RTL development. |
| [Soumabrata Roy](https://himalayas.app/@soumabrataroy) | Analog IC Design | India |  | Final-year ECE student focused on analogue IC design and VLSI sign-off, ready for onsemi-style power/analog teams. |
| [Akhilesh Ibrahimpet](https://himalayas.app/@akhileshibrahimpet) | Design Verification Engineer | India |  | I build SystemVerilog/UVM verification environments for RTL, memory controllers, and AMBA protocol designs. |

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