# Hire the best remote Senior Verification Engineer employees

Discover 42 remote Senior Verification Engineer workers who are looking for their next full-time, part-time or freelance opportunity on Himalayas.

Source: https://himalayas.app/talent/senior-verification-engineer

## 42 remote workers

| Person | Role | Location | Salary expectations | Intro |
| --- | --- | --- | --- | --- |
| [Srikar Maturi](https://himalayas.app/@srikarmaturi) | Hardware Engineer | India |  | Senior Hardware Engineer focused on UVM-based SoC verification, debug, and secure boot validation. |
| [Vidhi Radhanpura](https://himalayas.app/@vidhiradhanpura) | Verification Engineer | India |  | Verification engineer specializing in VLSI design and UVM-based functional verification with RTL expertise. |
| [Nitu Kumari](https://himalayas.app/@nitukumari) | Senior Verification Engineer | India |  | Experienced ASIC Verification Engineer specializing in pre-silicon validation. |
| [Keshava jaya ram Chitturi](https://himalayas.app/@keshavajayaramchittu) | Verification Engineer | India |  | Verification engineer specializing in UVM verification, FPGA validation, and debugging for camera ISP and AI accelerators. |
| [Andrew Chen](https://himalayas.app/@andrewchen4) | Fpga Engineer | United States |  | Senior FPGA/ASIC verification engineer specializing in UVM, constrained-random, coverage-driven closure, and high-speed protocol validation. |
| [Mahendar Mahi](https://himalayas.app/@mahendarmahi) | Verification Engineer | India |  | VLSI verification engineer specializing in UVM and protocol verification. |
| [Faisal Saeed Awan](https://himalayas.app/@faisalsaeedawan) | Verification Engineer | Pakistan |  | I’m a UVM ASIC/SoC Functional Verification Engineer focused on first-pass silicon. |
| [Ali Sajjad](https://himalayas.app/@alisajjad-dev) | Verification Engineer | Pakistan |  | RTL Design and Formal Verification engineer specializing in RISC-V and floating-point units. |
| [Battinapati Durga Manohar](https://himalayas.app/@battinapatidurgamano) | Verification Engineer | India |  | VLSI verification engineer skilled in SystemVerilog/UVM, delivering robust RTL and coverage-driven verification. |
| [Harshini Paka](https://himalayas.app/@harshinipaka) | Design Verification Engineer | India | 45k+ USD | I build verification and regression infrastructure for PCIe-to-AXI FPGA host interface subsystems. |
| [Nithu User](https://himalayas.app/@nithuuser) | Verification Engineer | India |  | Electronics/ECE graduate specializing in SystemVerilog UVM functional verification. |
| [Aman K](https://himalayas.app/@amank1) | Asic Verification Engineer | India |  | SoC/IP verification engineer specializing in SV/UVM, protocol VIPs, and debug automation. |
| [Rajesh Valipi](https://himalayas.app/@rajeshvalipi) | Design Verification Engineer | India |  | I’m a Design Verification Engineer specializing in UVM SystemVerilog protocol and VIP development. |
| [Ravindra Singh](https://himalayas.app/@ravindrasingh2) | Design Verification Engineer | Ireland |  | I build UVM testbenches and formal verification solutions for complex IP, subsystems, and SoCs. |
| [Akhilesh Ibrahimpet](https://himalayas.app/@akhileshibrahimpet) | Design Verification Engineer | India |  | I build SystemVerilog/UVM verification environments for RTL, memory controllers, and AMBA protocol designs. |
| [Aishwarya Subramanian](https://himalayas.app/@aishwaryasubramanian) | Senior Verification Engineer | India |  | Skilled design verification engineer focused on optimizing testbench performance. |
| [Lavanya-G4 Vlsi User](https://himalayas.app/@lavanya-g4vlsiuser) | Verification Engineer | India |  | Aspiring Design Verification Engineer experienced in Verilog, SystemVerilog and RTL verification. |
| [Sohaib El Aichi](https://himalayas.app/@sohaibelaichi) | Design Verification Engineer | Morocco | 60k+ USD | Senior Design Verification Engineer at AION Silicon, closing coverage on vision and automotive ADAS chips that reached tapeout. |
| [Chirag Dalsaniya](https://himalayas.app/@chiragdalsaniya) | Asic Verification Engineer | India | 1058k+ INR | I build and verify RTL designs using Verilog, SystemVerilog, UVM, and coverage-driven verification. |
| [Aditya Raut](https://himalayas.app/@adityaraut3) | Design Verification Engineer | India |  | I design and verify FPGA-based digital interfaces and high-speed arithmetic RTL. |

Page 1 of 3. Next page: [page 2](https://himalayas.app/talent/senior-verification-engineer.md?page=2)

To contact someone, message them from their profile with a Himalayas employer account: [Hire on Himalayas](https://himalayas.app/hire).