# Hire the best remote RTL Code Generation employees

Discover 39 remote RTL Code Generation workers who are looking for their next full-time, part-time or freelance opportunity on Himalayas.

Source: https://himalayas.app/talent/rtl-code-generation

## 39 remote workers

| Person | Role | Location | Salary expectations | Intro |
| --- | --- | --- | --- | --- |
| [Shri Sharan R](https://himalayas.app/@shrisharanrajaram) | Software Developer | India | 46k+ USD | Software Development Engineer at Amazon building React Native framework features for Vega OS. |
| [Pravimal Elipay](https://himalayas.app/@pravimalelipay) | RTL Design Engineer | India | 70k+ INR | RTL design engineer aspirant with software experience at i2oretail. |
| [veda s](https://himalayas.app/@vedas) | ASIC Design Engineer | India |  | RTL/ASIC Design Engineer specializing in RTL quality, CDC sign-off, and SoC integration. |
| [Ritesh Jadhav](https://himalayas.app/@riteshjadhav2) | RTL Design Engineer | India | 70k+ INR | RTL design engineer at Accenture who developed DMA, I3C, and SHA IPs and implemented I3C protocol features. |
| [Mohamed Elkomy](https://himalayas.app/@mohamedelkomy) | Front End Developer | Egypt | 30k+ USD | I build production React frontends for multilingual client applications. |
| [Wilberth Gutierrez](https://himalayas.app/@wilberthgutierrez) | VLSI Engineer | Costa Rica | 36k+ USD | VLSI Design & Verification Engineer at Rydev who developed a pipelined RISC-V SoC and reusable UVM verification environments. |
| [alissar almhaisen](https://himalayas.app/@alissaralmhaisen) | Front End Developer | Jordan | 60k+ USD | Front-End Developer on Awnak, an Arabic RTL platform built with Next.js and React, with an AI chatbot integrated through an API. |
| [Marwan Ahmed](https://himalayas.app/@marwanahmed2) | RTL Design and Verification Engineer | Egypt | 60k+ USD | Digital IC design and verification engineer with silicon tapeout experience, including a TinyECG arrhythmia classifier taped out to Sky130. |
| [Ponnitivalasa Manikantha](https://himalayas.app/@ponnitivalasamanikan) | RTL Design Engineer | India | 1259k+ INR | Aspiring RTL Design Engineer focused on VLSI, who optimized RTL timing and designed RISC-V processors. |
| [Abdullah Naser](https://himalayas.app/@abdullahnaser) | Front End Developer | Jordan |  | I build multilingual React and Next.js applications with production-ready user experiences. |
| [HARI MADDUKURI](https://himalayas.app/@harimaddukuri) | RTL Design Engineer | India | 70k-150k USD | I build RTL and FPGA solutions for radar, timing, and hardware validation. |
| [Davit Gharagyozyan](https://himalayas.app/@davitgharagyozyan) | Software Engineer | Armenia | 30k-35k USD | Software / EDA engineer specializing in C++ and Python for EDA. |
| [Aya Mydani](https://himalayas.app/@ayamydani) | Full Stack Developer | Turkey | 1030k+ TRY | Frontend Developer at OTO who built the frontend for an AI Rule Creator that turns natural-language input into shipping automation rules. |
| [Vidyasagar Belkatte](https://himalayas.app/@vidyasagarbelkatte) | Physical Design Engineer | India | 435k+ INR | Aspiring Physical Design Engineer trained in the RTL-to-GDSII flow; worked on a full-chip ASIC design using TSMC 65nm technology. |
| [Twaheer N](https://himalayas.app/@twaheern) | Design Verification Engineer | India | 140k+ INR | Design Verification Engineer at Saksham Semiconductors who developed RTL for 5+ IP blocks and achieved 98% functional coverage with a UVM testbench. |
| [Bhanu Naga Sarika Neelam](https://himalayas.app/@bhanunagasarikaneela) | Verification Engineer | India |  | RTL verification engineer focused on UVM-based functional coverage for ASIC/SoC. |
| [KANAN BAJAJ](https://himalayas.app/@kananbajaj1) | RTL Design Engineer | India |  | I build RTL, ASIC, and FPGA systems from Verilog design through implementation. |
| [Nithin P B](https://himalayas.app/@nithinpb) | DFT Engineer | India | 510k+ INR | DFT Verification Engineer at HCLTech building shift-left DFT automation and a production regression framework with a ~9× speedup. |
| [sayeekumar swaminathan](https://himalayas.app/@sayeekumarswaminatha) | RTL Design Engineer | India | 200k+ USD | I build and verify RTL processors, microarchitecture, and hardware test suites. |
| [nikhitha annthomas](https://himalayas.app/@nikhithaannthomas) | Physical Design Engineer | India |  | VLSI Physical Design Engineer delivering RTL-to-GDSII timing, PnR, and power-optimized SoCs. |

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To contact someone, message them from their profile with a Himalayas employer account: [Hire on Himalayas](https://himalayas.app/hire).